Compliant Printed Circuit Area Array Semiconductor Package
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Solution Overview
Problem
Traditional IC device packaging methods are costly, inflexible, and lack reworkability, with area array packaging being expensive and challenging for terminal pitch, thermal management, and reliability of solder joints, especially when multiple IC devices are integrated in a single package.
Innovation Solution
The use of additive printing processes allows for the direct writing of circuitry and dielectrics, enabling stress decoupling at terminal joints and embedding functions, reducing production costs and enhancing electrical performance by varying material sets layer-by-layer, and incorporating on-board electrical devices and circuitry planes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional photolithography and area array packaging are used, then terminal interconnection is achieved, but production cost increases and manufacturing complexity increases
Solution Approach 1:
The patent replaces traditional photolithography (optical/mechanical system) with direct digital printing technology. The printing process uses digital files to directly deposit conductive materials and dielectrics layer by layer, eliminating the need for photomasks, chemical etching, and complex lithography equipment. This substitution significantly reduces manufacturing cost and complexity while maintaining interconnect reliability through precise material placement.
Solution Approach 2:
The patent changes the manufacturing approach from subtractive (etching away material) to additive (depositing material directly). The direct printing process allows for precise control of material composition, layer thickness, and pattern geometry through digital parameter control. This enables cost-effective production of area array packages with reliable interconnections by optimizing material usage and reducing waste.
2Adaptability or versatility
If area array packaging with solder joints is used, then terminal compliance is achieved, but solder joint reliability deteriorates due to thermal expansion mismatch
Solution Approach 1:
The patent introduces a compliant underfill material as an intermediary between the rigid substrate and the solder joints. This underfill layer absorbs thermal expansion differences between the substrate and the IC device, preventing stress concentration at the solder joints. The compliant material maintains electrical compliance while protecting solder joint reliability from thermal mismatch damage.
Solution Approach 2:
The patent employs composite material structures in the substrate assembly, combining rigid support layers with compliant underfill materials. This composite approach provides both the structural integrity needed for area array packaging and the thermal compliance necessary to protect solder joints from reliability issues caused by thermal expansion mismatch.
3Productivity
If multiple IC devices are placed in a single package (SiP), then device integration increases, but package complexity and manufacturing difficulty increase
Solution Approach 1:
The patent uses direct digital printing to create modular, segmentable substrate structures that can accommodate multiple IC devices. The printing process allows for independent design and fabrication of different substrate regions, each optimized for specific device types or functions. This segmentation reduces overall package complexity by breaking down the multi-device integration into manageable, independently manufacturable modules.
Solution Approach 2:
The patent utilizes three-dimensional layering through direct printing to integrate multiple IC devices vertically within a compact package footprint. By building up conductive traces, dielectric layers, and contact structures in multiple stacked layers, the system achieves high device integration without proportionally increasing planar package complexity. The additive process naturally manages the spatial arrangement of multiple devices across different height levels.
4Reliability
If epoxy underfill is applied to protect solder joints, then joint protection improves, but reworkability deteriorates as connections become non-reworkable
Solution Approach 1:
The patent employs a compliant underfill material with dynamic mechanical properties that can reversibly deform under stress. Unlike rigid epoxy that permanently bonds and prevents rework, the compliant material allows for controlled separation and reattachment of the IC device. This dynamic behavior maintains joint protection during normal operation while enabling reworkability when needed, as the material can accommodate the mechanical stresses of removal and reinstallation.
Data Source
AI summary
An integrated circuit (IC) package for an IC device, and a method of making the same. The IC package includes an interconnect assembly with at least one printed compliant layer, a plurality of first contact members located along a first major surface, a plurality of second contact members located along a second major surface, and a plurality of printed conductive traces electrically coupling a plurality of the first and second contact members. The compliant layer is positioned to bias at least the first contact members against terminals on the IC device. Packaging substantially surrounds the IC device and the interconnect assembly. The second contact members are accessible from outside the packaging.