Component Carrier Via Structure With Asymmetric Baseline Etching
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Solution Overview
Problem
The challenge in manufacturing component carriers, such as printed circuit boards, is to create robust and reliable electrically conductive vertical through-connections (vias) while avoiding defects like voids and cracks caused by the baseline etch region during the via formation process, which affects the mechanical and electrical reliability of the carriers.
Innovation Solution
A component carrier design with a multi-layer stack featuring a higher total area of first baseline etch surfaces on one side and deeper second baseline etch surfaces on the opposing side, allowing for more controlled etching and reduced defect formation, resulting in more reliable via structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If baseline etching is performed to remove residues before via filling, then cleaning effectiveness is improved, but defect formation (voids and cracks) increases
Solution Approach 1:
The patent applies different etching depths to different regions of the conductive surface. The baseline etch creates localized etch features with controlled depth and geometry, providing cleaning effectiveness in specific areas while avoiding excessive etching that would cause defects. This localized approach allows optimization of cleaning in regions where residues are present while maintaining via reliability in other areas.
Solution Approach 2:
The patent controls the etching process by adjusting parameters such as etch depth, etch feature geometry, and etch distribution across the conductive surface. By optimizing these parameters, the process achieves sufficient residue removal while preventing the formation of defects that would compromise via reliability. The etch depth is controlled to be sufficient for cleaning but not so deep as to create void-prone conditions.
2Manufacturing precision
If deeper baseline etch regions are formed to ensure complete residue removal, then cleaning thoroughness is improved, but void and crack formation increases
Solution Approach 1:
Instead of applying uniform deep etching across all areas, the patent creates localized etch features with controlled depth. This ensures that residue removal is concentrated where needed while avoiding excessive etching in other regions that would lead to void and crack formation. The local quality approach allows differentiated treatment of different surface areas.
Solution Approach 2:
The patent converts the potentially harmful effect of deep etching into a beneficial controlled etch feature. By intentionally designing the etch geometry and depth, the process transforms what would be a defect-causing deep etch into a controlled feature that aids residue removal while preventing the formation of harmful voids and cracks. The controlled etch feature becomes a beneficial element in the via structure.
3Reliability
If asymmetric baseline etch surfaces are created with different total areas on opposite sides, then via reliability on one side is improved, but manufacturing complexity increases
Solution Approach 1:
The patent intentionally creates asymmetric baseline etch surfaces where the total area of etch features on the first side differs from the total area on the opposite side. This asymmetry is designed to optimize via reliability on each side according to specific electrical and mechanical requirements. The asymmetric configuration allows tailored via performance while the etch process itself remains relatively simple to implement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and robustness of via formation by minimizing defects and ensuring efficient electrical connections, while maintaining mechanical integrity and thermal management capabilities.
Implementation Method 1
During a cleaning process of the hole (for the via formation by filling) and the metal layer at the hole bottom, a baseline etch region within the surface of the metal layer can form
Data Source
Figure 1~4C
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AI summary
The present application provides a component carrier and a method of manufacture the same, the component carrier, comprising: a stack with a plurality of electrically insulating layer structures and one or more electrically conductive layer structures , the one or more electrically conductive layer structures comprise two opposed conductive surfaces ; a plurality of first vias , formed at a front side of the stack , the plurality of first vias is connected to one of the two opposed conductive surfaces through a respective first baseline etch surface ; and a plurality of second vias , formed at a back side of the stack, the front side is opposed to the back side , wherein the plurality of second vias is connected to the other one of the two opposed conductive surfaces through a respective second baseline etch surface . The total area defined by the first baseline etch surfaces is higher than the total area defined by the second baseline etch surfaces and the depth of at least one of the first baseline etch surfaces is lower than the depth of at least one of the second baseline etch surfaces.