Component Carrier Wiring Layout for Dense, Insulated Interconnects
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Solution Overview
Problem
The increasing miniaturization and power of electronic components on component carriers, along with the need for efficient heat removal and mechanical robustness, pose challenges in designing carriers that meet target requirements, particularly when surface mounting powerful components.
Innovation Solution
A component carrier design featuring a stack of electrically insulating and conductive layers with equidistant wiring elements and conductive areas, where each conductive area is spaced at least 5% of the wiring element's diameter from adjacent areas to ensure reliable electrical connectivity and prevent short circuits, while maintaining mechanical robustness and efficient heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If wiring elements are arranged in rows with small spacing to increase component density, then the quantity of wiring elements per area increases, but the risk of electrical breakdown and short circuits increases
Solution Approach 1:
The patent introduces a third dimension by stacking multiple wiring planes vertically. Wiring elements are arranged in rows on different planes at different heights, allowing high density interconnections without requiring small lateral spacing between adjacent wiring elements on the same plane. This vertical stacking enables increased quantity of wiring elements per area while maintaining safe spacing on each individual plane.
Solution Approach 2:
The patent uses conductive areas (pads) as intermediaries between wiring elements on different planes. These conductive areas provide robust electrical connection points and are spaced apart laterally, preventing direct close proximity between wiring elements from different planes. The conductive areas act as mediators that enable high-density interconnections while maintaining electrical reliability through adequate spacing.
2Area of stationary object
If conductive areas are placed close together to reduce carrier size, then the area of the component carrier decreases, but the risk of electrical breakdown between adjacent conductive areas increases
Solution Approach 1:
The patent utilizes vertical stacking of multiple wiring planes with conductive areas at different heights. This allows conductive areas to be positioned close together in the lateral plane while maintaining adequate vertical separation through the insulating layer structures. The third dimension enables reduced carrier area while preserving electrical insulation between adjacent conductive areas through sufficient vertical spacing.
3Adaptability or versatility
If powerful electronic components are surface mounted to increase functionality, then the product functionality increases, but the heat generation and thermal management challenges increase
Solution Approach 1:
The patent divides the component carrier into multiple stacked wiring planes separated by insulating layer structures. This segmentation creates distinct thermal zones and pathways, allowing heat from surface-mounted powerful components to be dissipated through multiple routes via the distributed wiring elements and conductive areas across different planes, rather than concentrating heat in a single plane.
Data Source
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AI summary
A component carrier (100) which comprises a stack (102) comprising at least two electrically insulating layer structures (106, 106', 106") and at least one electrically conductive layer structure (104, 104', 104"), a plurality of wiring elements (108) provided in one of the at least two electrically insulating layer structures (106), said plurality of wiring elements (108) being arranged in a wiring plane (162) to form a first row (110) of equidistant wiring elements (108) arranged along a straight direction within the wiring plane (162), and a second row (112) of equidistant wiring elements (108) arranged along the straight direction within the wiring plane (162), a plurality of further wiring elements (108') provided in another of the at least two electrically insulating layer structures (106'), wherein the at least one electrically conductive layer structure (104, 104', 104") comprises several conductive areas (111) being electrically insulated with respect to each other, each of said conductive areas (111) being connected to at least one of the plurality of wiring elements (108) and to at least one of the plurality of further wiring elements (108'), and wherein each of the conductive areas (111) of the at least one electrically conductive layer structure (104, 104', 104") is spaced by a distance (d) from a respective conductive area (111) connected to an adjacent wiring element (108, 108'), wherein said distance (d) is at least 5% of a diameter (D1) of the wiring element (108, 108').