Electronic Component Package With Vertical Interconnects for Heat Dissipation
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Solution Overview
Problem
Existing electronic component packaging technologies, such as lead frame and flip-chip packaging, face challenges in miniaturization, increased complexity of I/O connections, and heat dissipation, which limit their ability to efficiently package high-voltage or high-current chips.
Innovation Solution
The proposed electronic component package integrates a high-voltage transistor semiconductor die and a control circuit bare chip using a metal layer with external terminals and vertical connection structures, replacing traditional lead frames and enhancing heat dissipation and connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If lead frame packaging technology is used to provide electrical connections through electrical leads, then electrical connectivity is achieved, but the spatial location of chip electrical connection is limited and wiring area on printed circuit boards increases
Solution Approach 1:
The patent transitions from planar lead frame connections to three-dimensional vertical connections through conductive pillars extending through the substrate. This dimensional change allows electrical connections to be made in the vertical direction rather than requiring extensive lateral wiring, thereby reducing the wiring area on printed circuit boards while maintaining electrical connectivity.
2Volume of moving object
If packaging technology increases in density and miniaturization, then component size is reduced, but the number of I/O connection pins increases and becomes more complex
Solution Approach 1:
The patent segments the I/O connections into multiple independent conductive pillars that can be individually configured and connected to different chip pads. This segmentation allows each pillar to serve a specific connection function, simplifying the overall complexity by breaking down the complex I/O network into manageable, modular vertical connection elements while enabling miniaturization.
3Adaptability or versatility
If flip-chip packaging technology is used for multi-chip packaging, then chips are connected face-down, but manufacturing cost increases and throughput is reduced due to complicated manufacturing process
Solution Approach 1:
The patent uses a substrate with replicated conductive pillar structures that can accommodate multiple chips in various configurations. Instead of requiring complex flip-chip alignment processes, the substrate provides a standardized template that simplifies the manufacturing process, enabling high-volume production while maintaining multi-chip packaging versatility. The conductive pillars serve as pre-configured connection points that reduce assembly complexity.
Data Source
AI summary
The present invention relates to an electronic component package and a manufacturing method therefor. In an embodiment, the electronic component package comprises: a first metal layer, a high-voltage transistor semiconductor die, a first molding compound layer, a second metal layer, a first vertical connection structure, a second vertical connection structure, a control circuit bare chip, and a second molding compound layer. In the electronic component package of the present invention, a lead frame and electrical leads are replaced with the metal layers and the vertical connection structures, so that the position of the electrical connection of the chip is more flexible and the heat dissipation effect is better. Compared with the lead frames and the electrical leads, the electronic component package of the present disclosure is more suitable for packaging high-voltage or high-current chips.