Composable Network Processing Pipeline with Fixed-Function Logic
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Solution Overview
Problem
Existing network processing device architectures face challenges in achieving optimal data flow and performance due to limitations in resource availability and flexibility, particularly in scenarios requiring hardware offload functions.
Innovation Solution
The implementation of a composable processing pipeline with a configurable programmable per-op component close-coupled with programmable logic and software, which includes both FPGA and ASIC per-op components, allows for flexible invocation of processing functions via uniform APIs, optimizing data flow for various use cases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGA-based SmartNICs are used to provide programmability comparable to software, then programmability is improved, but performance and efficiency are compromised compared to hardware
Solution Approach 1:
The processing pipeline is divided into multiple stages with different implementation approaches. Early stages use fixed-function logic components for high-performance hardware-like processing, while later stages use programmable logic components for flexible software-like processing. This segmentation allows each stage to be optimized for its specific requirements, achieving both high performance and programmability.
Solution Approach 2:
Different portions of the processing pipeline are implemented with different qualities - some portions use fixed-function logic for speed-critical operations, while other portions use programmable logic for flexibility-critical operations. This local differentiation of implementation quality allows the system to achieve both high performance and programmability in appropriate locations.
2Productivity
If ASIC-based SmartNICs are used to provide cost-effective performance, then performance is improved, but flexibility is limited compared to FPGA-based solutions
Solution Approach 1:
The system merges fixed-function logic components (providing ASIC-like performance) with programmable logic components (providing FPGA-like flexibility) into a unified processing pipeline. This combination allows the system to achieve both high performance and flexibility by leveraging the strengths of both approaches in appropriate processing stages.
3Productivity
If a composable processing pipeline with both FPGA and ASIC per-op components is implemented, then data flow optimization is improved, but device complexity increases
Solution Approach 1:
The processing pipeline is designed to be dynamically configurable, allowing different combinations of fixed-function and programmable logic components to be activated based on the specific processing requirements. This dynamic configurability enables optimization for different data flow scenarios while managing complexity through selective activation of pipeline stages.
Data Source
AI summary
Implementations of architectures for network processing using a fixed-function logic per-op component close-coupled with programmable logic and software are provided. One aspect provides an integrated circuit device for network processing, the device comprising a composable processing pipeline that includes a programmable per-op component and a fixed-function logic per-op component that is close-coupled with programmable logic and software. The device further comprises a compute complex component comprising processing circuitry implementing the software for controlling the programmable per-op component and the fixed-function logic per-op component, wherein for a first processing pipeline, the processing circuitry is configured to perform a first function using the programmable per-op component, and for a second processing pipeline, the processing circuitry is configured to perform a second function using the fixed-function logic per-op component.