Composable Neural Network Kernels for Tensor Operations

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Solution Overview

Problem

Modern neural networks face challenges in achieving efficient computation due to the complexity of tensor operations and varying dimensionalities, sizes, and memory data layouts, which complicates hardware and software optimization across different hardware platforms.

Innovation Solution

A technique for manipulating generic tensors is introduced, allowing for operations on tensor descriptors and raw data, including slicing, merging, embedding, and reordering, to facilitate efficient computation by converting operations like convolution into General Matrix Multiplication (GEMM), enabling flexible and efficient processing across various hardware architectures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If complex tensor operations with varying dimensionalities and data layouts are performed directly, then computational accuracy is maintained, but computational efficiency and hardware adaptability deteriorate

Engineering Contradiction:
Improvecomputational efficiencyVSAvoidoperation complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments complex tensor operations into a standardized sequence of primitive operations (transposition, permutation, slicing, merging, embedding). Each primitive operation is independently optimized and can be efficiently mapped to different hardware architectures, thereby improving computational efficiency while maintaining manageable operation complexity through modular decomposition.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent creates a universal tensor operation framework that can handle various tensor operations (convolution, matrix multiplication, etc.) through a common set of primitive operations. This universal approach allows the same operation sequence to be efficiently executed on different hardware platforms (CPU, GPU, FPGA, ASIC), improving productivity across diverse hardware without requiring separate optimized implementations for each operation type.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Speed

If specialized hardware is designed for specific neural network operations, then computational speed is improved, but hardware versatility and adaptability to different operations deteriorate

Engineering Contradiction:
Improvecomputational speedVSAvoidhardware adaptability
Core Design Contradiction:
SpeedVSAdaptability or versatility

Solution Approach 1:

The patent develops a universal tensor operation framework where a single hardware architecture can efficiently execute multiple types of neural network operations through standardized primitive operations. The framework translates diverse operations (convolution, GEMM, etc.) into a common intermediate representation that can be executed on the same hardware, achieving both high speed through optimization and high versatility through adaptability to different operation types.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent uses parameter-based configuration to adapt the same hardware architecture to different operations. By changing parameters such as tensor dimensions, data layouts, and operation sequences in the standardized framework, the hardware can efficiently execute different neural network operations without physical reconfiguration, maintaining both speed and versatility.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If tensor operations are optimized for specific hardware architectures, then performance on that hardware is improved, but portability to other hardware platforms deteriorates

Engineering Contradiction:
Improvehardware performanceVSAvoidplatform portability
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent creates a hardware-agnostic tensor operation framework that defines standardized primitive operations and a common intermediate representation. This universal framework can be compiled or translated to target different hardware architectures (CPU, GPU, FPGA, ASIC) while maintaining optimized performance on each platform. The separation between the universal operation definition and hardware-specific implementation enables both high performance and broad portability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Speed

If high-dimensional tensor operations are performed with detailed data layout control, then computational precision is maintained, but memory access efficiency and processing speed deteriorate

Engineering Contradiction:
Improveprocessing speedVSAvoiddata layout complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent segments high-dimensional tensor operations into lower-dimensional primitive operations that operate on smaller data subsets with simpler layouts. By decomposing complex high-dimensional operations into sequences of transposition, slicing, and merging operations on lower-dimensional tensors, the framework achieves better memory access patterns and processing speed while maintaining computational precision through the systematic composition of these segmented operations.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12190225B2Composable neural network kernels
Publication Date: 2025.01.07 ADVANCED MICRO DEVICES INC
  • US12190225B2 patent drawing
  • US12190225B2 patent drawing
  • US12190225B2 patent drawing

AI summary

A technique for manipulating a generic tensor is provided. The technique includes receiving a first request to perform a first operation on a generic tensor descriptor associated with the generic tensor, responsive to the first request, performing the first operation on the generic tensor descriptor, receiving a second request to perform a second operation on generic tensor raw data associated with the generic tensor, and responsive to the second request, performing the second operation on the generic tensor raw data.