Composite Blocking Dielectric for 3D NAND Memory
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Solution Overview
Problem
Three-dimensional NAND memory devices face challenges in achieving robust read disturb immunity and long retention with excellent scaling capabilities due to limitations in the configuration of flat memory cells with vertical tunneling dielectrics.
Innovation Solution
A three-dimensional memory device is designed with alternating stacks of insulating and electrically conductive strips over a substrate, featuring memory stack structures with a composite blocking dielectric layer comprising a first dipole-containing blocking dielectric layer stack, a homogeneous blocking dielectric layer, and a second dipole-containing blocking dielectric layer stack, which enhances charge retention and programming efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional blocking dielectric layer is used in flat memory cells, then the device structure is simple, but read disturb immunity and retention are insufficient
Solution Approach 1:
The blocking dielectric layer is segmented into multiple distinct layers: a first dipole-containing blocking dielectric layer, a second dipole-containing blocking dielectric layer, and an optional third non-dipole blocking dielectric layer positioned between them. This segmentation allows each layer to perform specific functions, with the dipole layers providing enhanced charge retention and the intermediate layer preventing charge leakage, thereby improving read disturb immunity and retention without excessive complexity
Solution Approach 2:
The blocking dielectric structure employs composite materials with different properties: dipole-containing materials (such as aluminum oxide or zirconium oxide) are combined with non-dipole materials (such as silicon oxide). The dipole materials provide strong charge trapping capability while the non-dipole material provides electrical isolation, creating a composite structure that simultaneously improves retention and prevents charge leakage between cells
2Reliability
If the blocking dielectric layer is made thicker to improve charge retention, then retention is improved, but programming and erase voltages increase
Solution Approach 1:
The invention changes the material parameters of the blocking dielectric layer by introducing dipole-containing materials with specific dielectric constants and charge trapping characteristics. The dipole layers have high electron affinity and can trap charges at lower voltage thresholds, allowing thick blocking dielectric structures to achieve charge retention without requiring proportionally higher programming and erase voltages. The dipole moments in these materials create internal electric fields that assist charge injection at lower applied voltages
Solution Approach 2:
The composite blocking dielectric structure combines dipole-containing materials (providing charge retention) with non-dipole materials (providing electrical isolation). This composite approach allows the overall structure to be thicker for better retention while the dipole layers' material properties enable charge trapping at lower voltage thresholds, preventing the linear increase in programming/erase voltages that would normally accompany increased thickness
3Productivity
If scaling is increased to improve device density, then capacity is improved, but read disturb immunity and retention deteriorate
Solution Approach 1:
The composite blocking dielectric structure maintains effective charge isolation even as overall device dimensions are reduced for scaling. The dipole-containing layers provide strong charge trapping capability that is less sensitive to dimensional reduction, while the intermediate non-dipole layer maintains electrical isolation between adjacent memory cells. This composite approach allows the blocking dielectric to function effectively at smaller scales where conventional single-layer structures would fail to provide adequate read disturb immunity
Solution Approach 2:
The invention applies different material qualities to different regions of the blocking dielectric structure: dipole-containing materials are positioned where charge trapping is most critical (adjacent to the charge storage layer), while non-dipole materials are positioned where electrical isolation is most critical (between adjacent cells). This local optimization of material properties ensures that each region performs its specific function effectively, maintaining read disturb immunity and retention even as overall device size is reduced for higher density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides improved read disturb immunity, long retention, and excellent scaling capabilities by modifying the blocking dielectric layer structure, allowing for lower programming and erase voltages and superior threshold voltage characteristics.
Implementation Method 1
a first dipole-containing blocking dielectric layer stack, a homogeneous blocking dielectric layer, and a second dipole-containing blocking dielectric layer stack
Data Source
AI summary
A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips located over a substrate and laterally spaced apart among one another by line trenches which laterally extend along a first horizontal direction and are spaced apart along a second horizontal direction, and memory stack structures arranged in rows extending along the first horizontal direction. Each row of memory stack structures is located on a respective sidewall of the line trenches. Each of the memory stack structures includes a vertical semiconductor channel, a tunneling dielectric contacting the vertical semiconductor channel, a charge storage layer contacting the tunneling dielectric, and a composite blocking dielectric. The composite blocking dielectric includes a first dipole-containing blocking dielectric layer stack, a homogeneous blocking dielectric layer, and a second dipole-containing blocking dielectric layer stack.