Composite Interconnect Bridges for 3D IC Power Delivery Limits
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Solution Overview
Problem
The challenge in 3D stacked semiconductor packages is the escalating power integrity requirements for high-performance computing devices, particularly due to constraints on maximum current (Imax) distribution caused by reduced interconnect geometries such as C4 solder bumps, micro-bumps, and through-silicon-vias, which pose reliability risks and hinder device miniaturization and performance.
Innovation Solution
A semiconductor package design featuring first and second interconnect bridges with a power corridor between them, filled with dielectric material, which forms a composite bridge with vertical interconnects, enhancing power delivery by increasing metal volume and reducing DC resistance, thereby improving Imax capacity and allowing for higher power ratings and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If reduced interconnect geometries (C4 solder bumps, micro-bumps, TSVs) are used for package miniaturization, then package footprint is reduced, but maximum current (Imax) capacity and reliability deteriorate
Solution Approach 1:
The patent transitions from planar 2D interconnect layouts to 3D vertical interconnect structures. By stacking multiple interconnect layers vertically and creating three-dimensional composite bridges with power corridors extending through multiple levels, the design achieves higher current capacity within a reduced footprint by utilizing the vertical dimension for power delivery.
Solution Approach 2:
The patent employs composite bridge structures combining different materials and interconnect types (C4 bumps, micro-bumps, TSVs, and power corridor materials) to create hybrid interconnect systems. These composite structures optimize both current carrying capacity and mechanical reliability while maintaining miniaturized form factors.
2Area of stationary object
If reduced interconnect geometries are used, then package form factor is miniaturized, but power delivery performance deteriorates
Solution Approach 1:
The patent implements multi-layer power corridors that extend vertically through stacked interconnect levels, creating 3D power delivery pathways. This vertical dimensionality allows increased power delivery capacity without expanding the planar footprint, as power can be delivered through multiple stacked conductive layers simultaneously.
Solution Approach 2:
The power delivery network is segmented into multiple vertical channels and power corridors distributed across different interconnect levels. This segmentation allows parallel power delivery paths, increasing total power capacity while maintaining a compact form factor through efficient spatial distribution.
3Device complexity
If conventional power delivery networks are used in 3D stacked packages, then device complexity is maintained, but power integrity deteriorates
Solution Approach 1:
The patent merges power delivery and signal interconnect functions into integrated composite bridge structures. By combining power corridors with signal TSVs and interconnect elements into unified 3D assemblies, the design achieves improved power integrity through reduced inductance and enhanced current distribution while managing complexity through functional integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves improved power delivery performance with reduced DC resistance and increased Imax capacity, enabling higher power ratings and performance for computer processors and graphic silicon devices, while also facilitating device miniaturization and reducing package warpage.
Implementation Method 1
enhancing power delivery by increasing metal volume and reducing DC resistance
Data Source
AI summary
The present disclosure is directed to semiconductor packages incorporating composite or hybrid bridges that include first and second interconnect bridges positioned on a substrate and a power corridor with a plurality of vertical channels positioned on the substrate between the first and second interconnect bridges, wherein the power corridor integrally joins the first interconnect bridge to the second interconnect bridge.