Composite Bump-on-Lead Interconnect for Semiconductor Routing Density
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Solution Overview
Problem
Conventional flipchip interconnection methods in semiconductor devices result in high costs due to the need for multilayer substrates and introduce electrical parasitics, limiting routing density and package performance.
Innovation Solution
The development of a composite bump-on-lead interconnection method that eliminates the need for capture pads and solder masks by using a composite interconnect with a non-fusible portion connected to the semiconductor die and a fusible portion connected to the substrate, allowing for higher routing density and reduced parasitics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional flipchip interconnection methods are used, then reliable electrical connections are achieved, but device complexity and manufacturing cost increase due to the need for multilayer substrates and solder masks
Solution Approach 1:
The invention extracts and eliminates the solder mask layer from the conventional flipchip interconnection structure. By using a composite bump structure where the fusible material is contained within the bump itself rather than relying on a solder mask to confine molten solder, the patent removes this unnecessary layer, simplifying the overall device structure while maintaining reliable electrical connections
Solution Approach 2:
The invention segments the bump structure into distinct functional portions: a non-fusible portion providing structural support and electrical connection to the die, and a fusible portion containing the molten solder for bonding to the substrate. This segmentation allows each portion to be optimized for its specific function while eliminating the need for additional confining structures
2Reliability
If conventional flipchip interconnection methods are used, then electrical connections are established, but routing density is limited due to the presence of capture pads and solder masks
Solution Approach 1:
The invention removes the solder mask layer that traditionally confines molten solder during reflow. By incorporating the fusible material directly within the composite bump structure, the patent eliminates the solder mask's space-consuming presence, thereby increasing the density of interconnect sites that can be packed into a given area
Solution Approach 2:
The composite bump structure applies local quality by concentrating the fusible material only where needed (in the portion that contacts the substrate) while keeping the upper portion non-fusible for die attachment. This localized functionality allows for more efficient space utilization and higher routing density compared to conventional uniform bump structures
3Reliability
If conventional flipchip interconnection methods are used, then electrical connections are formed, but electrical parasitics increase, limiting package performance
Solution Approach 1:
The composite bump structure segments the electrical connection path into distinct portions with optimized properties. The non-fusible portion provides a low-inductance mechanical and electrical bond to the die, while the fusible portion creates a controlled bonding interface with the substrate. This segmentation reduces overall electrical parasitics compared to conventional single-material bumps
Solution Approach 2:
The invention uses composite materials by combining fusible and non-fusible portions within a single bump structure. This composite approach allows optimization of electrical properties at each interface, reducing electrical parasitics while maintaining reliable connections. The different material properties enable better control over bonding characteristics and electrical performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases routing density and reduces electrical parasitics, leading to improved package performance and lower costs by eliminating the need for multilayer substrates and solder masks, while maintaining reliable electrical connections.
Implementation Method 1
fusible portion connected to the trace on the substrate
Implementation Method 2
composite bump material is reflowed to form a composite interconnect
Data Source
AI summary
A semiconductor device has a semiconductor die mounted to a substrate with a plurality of composite interconnects formed between interconnect sites on the substrate and bump pads on the die. The interconnect sites are part of traces formed on the substrate. The interconnect site has a width between 1.0 and 1.2 times a width of the trace. The composite interconnect is tapered. The composite interconnects have a fusible portion connected to the interconnect site and non-fusible portion connected to the bump pad. The non-fusible portion can be gold, copper, nickel, lead solder, or lead-tin alloy. The fusible portion can be tin, lead-free alloy, tin-silver alloy, tin-silver-copper alloy, tin-silver-indium alloy, eutectic solder, or other tin alloys with silver, copper, or lead. An underfill material is deposited between the semiconductor die and substrate. A finish such as Cu-OSP can be formed over the substrate.