Composite Ceramic Capacitor Noise Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Multilayer ceramic capacitors generate acoustic noise due to vibrations, which is a concern in modern electronic devices, and existing studies on using ceramic chips to mitigate this noise lack specific insights into the optimal size and mounting method for effective noise reduction.
Innovation Solution
A composite electronic component is designed with a multilayer ceramic capacitor and a ceramic chip, where the ceramic chip is coupled below the capacitor, with specific thickness and width ratios (1.6≤T1/T2≤3.5 and 0.8≤T1/W2≤1.2) to minimize acoustic noise and improve mounting reliability, using a ceramic material like alumina that does not deform elastically to block vibrations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a ceramic chip is coupled below the multilayer ceramic capacitor to reduce acoustic noise, then acoustic noise is reduced, but the device complexity increases
Solution Approach 1:
A ceramic chip is introduced as an intermediary component between the multilayer ceramic capacitor and the mounting board. This ceramic chip acts as a mediator to block the transmission path of vibrations from the capacitor to the board, thereby reducing acoustic noise while maintaining a relatively simple overall structure
Solution Approach 2:
The mounting structure is segmented into distinct functional components: the multilayer ceramic capacitor, the ceramic chip, and the mounting board. By dividing the system into separate segments with specific functions, the vibration isolation function is achieved without requiring complex integrated solutions
2Object-affected harmful factors
If the ceramic chip size is increased to improve noise reduction, then acoustic noise reduction improves, but the mounting reliability decreases
Solution Approach 1:
The patent optimizes specific dimensional parameters of the ceramic chip, including its thickness and width, to achieve the best balance between noise reduction and mounting reliability. By carefully controlling these parameters, the ceramic chip effectively blocks vibrations while maintaining proper mechanical connection and alignment
3Volume of moving object
If the multilayer ceramic capacitor size is reduced for miniaturization, then device miniaturization is achieved, but acoustic noise increases
Solution Approach 1:
The patent addresses the acoustic noise issue by introducing a solution in the vertical dimension (thickness direction) rather than increasing the horizontal footprint. The ceramic chip is positioned below the capacitor in the thickness direction, allowing noise reduction without increasing the overall device area, thus maintaining miniaturization benefits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces acoustic noise and enhances the mounting failure rate by optimizing the size ratios of the components, ensuring a balance between noise reduction and mechanical stability.
Implementation Method 1
a ceramic chip disposed below the multilayer ceramic capacitor and comprising a second ceramic body including ceramic
Data Source
AI summary
A composite electronic component includes a composite body including a multilayer ceramic capacitor and a ceramic chip coupled to each other. The multilayer ceramic capacitor includes a first ceramic body in which dielectric layers and internal electrodes disposed to face each other with one of the dielectric layers interposed therebetween are stacked, and first and second external electrodes disposed on opposite end portions of the first ceramic body, respectively. The ceramic chip is disposed below the multilayer ceramic capacitor, and includes a second ceramic body including ceramic and first and second terminal electrodes disposed on opposite end portions of the second ceramic body, respectively, and connected to the first and second external electrodes, respectively. A ratio (T1/T2) of a thickness (T1) of the multilayer ceramic capacitor to a thickness (T2) of the ceramic chip satisfies 1.6≤(T1/T2)≤3.5.