Composite Cell Layout Engine for Analog IC Design
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Solution Overview
Problem
The complexity of integrated circuit (IC) design, particularly for analog and mixed signal IC devices, is hindered by the time-consuming and resource-intensive process of searching through numerous layout scenarios to find a satisfactory and optimum layout, due to the limitations of existing IC design systems as feature sizes shrink and complexity increases.
Innovation Solution
The introduction of a design engine that transforms layout constraints into composite cells, allowing for the generation of layout scenarios in conformance with these constraints, thereby narrowing down the search space, and utilizing composite cells at multiple hierarchical levels to recursively reduce the number of possible scenarios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional automated layout tools search through thousands or millions of trial instantiations at the basic primitive cell level, then a satisfactory layout scenario can be identified, but significant computational resources and time are required
Solution Approach 1:
The layout search process is segmented into two distinct phases: a global optimization phase that searches at the composite cell level to identify promising layout scenarios, and a local optimization phase that refines scenarios at the primitive cell level. This segmentation reduces the overall search space and computational requirements while maintaining layout quality.
Solution Approach 2:
The invention introduces a hierarchical dimension to the layout search process by operating at multiple levels of abstraction (composite cell level and primitive cell level). This dimensional change allows the system to efficiently explore the design space globally before focusing on local details, significantly reducing search time.
2Device complexity
If the complexity of integrated circuits increases and feature sizes shrink, then design capabilities are pushed to limits, but existing IC design systems become limiting factors
Solution Approach 1:
The design system is segmented into hierarchical levels (composite cells and primitive cells) that can independently handle different aspects of complexity. This allows the system to manage increasingly complex IC designs by breaking them down into manageable hierarchical components without overwhelming computational resources.
Solution Approach 2:
Global optimization at the composite cell level performs preliminary actions to establish a reduced search space before local optimization begins. This preliminary action prepares the design system to efficiently handle complex circuits by pre-identifying promising layout scenarios, thereby improving adaptability to increasing device complexity.
3Reliability
If automated layout tools perform global optimization by searching through numerous trial instantiations, then layout constraints can be satisfied, but the vast amount of searching requires significant computational resources
Solution Approach 1:
The constraint satisfaction process is segmented across hierarchical levels, with global optimization at the composite cell level performing preliminary constraint checking and local optimization at the primitive cell level refining solutions. This segmentation ensures constraint conformance while reducing the computational energy required by eliminating infeasible scenarios early in the design process.
Solution Approach 2:
Global optimization performs preliminary actions to identify and eliminate layout scenarios that cannot satisfy constraints before local optimization begins. This preliminary constraint validation reduces the number of scenarios requiring full computational analysis, thereby reducing overall computational resource requirements while maintaining reliability.
Data Source
AI summary
Exemplary systems and methods of laying out integrated circuits are disclosed. The systems include a layout application configured to place geometries in conformance with layout constraints transformed into composite cells. A composite cell defines a relationship between one or more cells, such as parameterized cells, and is independent of the physical topology of the cells. The exemplary systems are configured to use the composite cells to restrict a number of possible layout scenarios by generating a first layout scenario in conformance with the composite cell implementations, and to thereafter generate a second layout scenario in conformance with the constraints on all cells within the first layout scenario. Embodiments of the present invention are particularly suited to the layout of analog and mixed signal integrated circuits resulting in faster, more flexible, and more efficient layout as compared with conventional techniques which require the layout application to search through a much broader set of possible scenarios.