Composite Semiconductor Channel for 3D Memory Dopant Control
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Solution Overview
Problem
In three-dimensional memory devices with horizontal source contact layers, controlling the diffusion of n-type dopants into vertical semiconductor channels is challenging due to the large grain size of polysilicon material and varying grain boundary orientations, leading to uneven dopant distribution and diffuse p-n junctions.
Innovation Solution
A composite semiconductor channel with different dopant concentrations and grain sizes is used, featuring a pedestal channel portion with high dopant concentration and a vertical channel with lower dopant concentration, controlled by a source contact layer to manage n-type dopant diffusion and improve transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a horizontal source contact layer is used in three-dimensional memory devices, then the device structure is simplified and manufacturing is easier, but the diffusion of n-type dopants into vertical semiconductor channels becomes difficult to control due to large grain size and varying grain boundary orientations
Solution Approach 1:
The semiconductor channel is segmented into two distinct regions: a pedestal channel portion with high dopant concentration and a vertical channel portion with low or no dopant concentration. This segmentation allows different dopant concentrations in different regions, enabling precise control over dopant diffusion while maintaining the horizontal source contact structure.
Solution Approach 2:
Different regions of the semiconductor channel are assigned different dopant concentrations tailored to their specific functional requirements. The pedestal channel portion receives high dopant concentration for strong electrical contact, while the vertical channel portion maintains low or zero dopant concentration for controlled diffusion and sharp junction formation.
2Ease of manufacture
If polysilicon material with large grain size is used in the vertical semiconductor channel, then the material is easier to deposit, but the dopant diffusion becomes uneven due to varying grain boundary orientations
Solution Approach 1:
The vertical channel portion is extracted from the dopant diffusion process entirely, maintaining low or zero dopant concentration. This removes the harmful effect of uncontrolled dopant diffusion through grain boundaries while preserving the ease of polysilicon deposition. The dopant diffusion is confined only to the pedestal channel portion where it is needed.
3Reliability
If high dopant concentration is applied throughout the entire vertical semiconductor channel, then electrical conductivity is improved, but the p-n junction becomes diffuse and transistor performance deteriorates
Solution Approach 1:
High dopant concentration is applied locally only to the pedestal channel portion where electrical conductivity is critical for contact formation. The vertical channel portion maintains low or zero dopant concentration, creating a sharp dopant concentration gradient that forms an abrupt p-n junction at the interface between the two regions.
Solution Approach 2:
The channel is segmented into dopant-rich and dopant-poor regions, allowing simultaneous optimization of electrical conductivity in the contact region and junction abruptness in the channel region. This spatial separation of dopant concentrations resolves the contradiction between conductivity and junction sharpness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved source side select transistor performance, including enhanced on/off ratio and reduced gate-induced drain leakage during erase operations, by creating a more abrupt junction and controlling dopant diffusion effectively.
Implementation Method 1
controlling the diffusion of n-type dopants into vertical semiconductor channels
Implementation Method 2
A composite semiconductor channel with different dopant concentrations and grain sizes is used, featuring a pedestal channel portion with high dopant concentration and a vertical channel with lower dopant concentration, controlled by a source contact layer to manage n-type dopant diffusion
Data Source
AI summary
A three-dimensional memory device includes a source contact layer overlying a substrate, an alternating stack of insulating layers and electrically conductive layers located overlying the source contact layer, and a memory opening fill structure located within a memory opening extending through the alternating stack and the source contact layer. The memory opening fill structure includes a composite semiconductor channel and a memory film laterally surrounding the composite semiconductor channel. The composite semiconductor channel includes a pedestal channel portion having controlled distribution of n-type dopants that diffuse from the source contact layer with a lower diffusion rate provided by carbon doping and smaller grain sizes, or has arsenic doping providing limited diffusion into the vertical semiconductor channel. The vertical semiconductor channel has large grain sizes to provide high charge carrier mobility, and is free of or includes only a low concentration of carbon atoms and n-type dopants therein.