Composite Chip-Substrate Packaging With Solder-Free Thermal Paths

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Solution Overview

Problem

Existing semiconductor device packaging technologies face challenges in achieving high electrical and thermal performance, reliability, and cost-effective manufacturing while ensuring versatile product mountability.

Innovation Solution

A method involving the formation of metal structures in a dielectric inorganic substrate wafer, bonding a semiconductor wafer to this substrate, and separating it into composite chips, which includes connecting electrodes to the metal structures without solder, enhancing thermal conductivity and electrical interconnects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional packaging technologies are used, then manufacturing processes are simpler, but electrical and thermal performance are insufficient

Engineering Contradiction:

Improveelectrical and thermal performanceVSAvoidpackaging structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the substrate and carrier wafer into a single integrated composite structure. The substrate includes integrated circuitry, while the carrier wafer provides mechanical support and electrical interconnects, eliminating the need for separate packaging components and achieving both high performance and manufacturing efficiency

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The invention uses a composite structure combining different materials: the substrate (e.g., semiconductor material) and the carrier wafer (e.g., ceramic or polymer) are bonded together to create a composite wafer that leverages the advantages of each material for optimal electrical, thermal, and mechanical performance

Inventive Principle:

Principle #40Composite materials

2Reliability

If high performance packaging is achieved, then electrical and thermal performance improve, but manufacturing costs increase

Engineering Contradiction:

Improveelectrical and thermal performanceVSAvoidmanufacturing cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The substrate and carrier wafer are prepared and pre-bonded in a wafer-fabrication step before chip separation. This preliminary action allows subsequent chip packaging to be performed efficiently after wafer-level processing, reducing overall manufacturing costs while maintaining high performance

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The carrier wafer serves multiple functions: providing mechanical support, establishing electrical interconnects, and enabling thermal management. This multi-functionality eliminates the need for separate components, reducing material costs and simplifying the manufacturing process

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Reliability

If conventional interconnect technology is used, then manufacturing is easier, but electrical and thermal performance are limited

Engineering Contradiction:

Improveelectrical and thermal performanceVSAvoidinterconnect structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates the solder layer from the interconnect structure. Direct bonding between the substrate and carrier wafer creates solder-free electrical and thermal pathways, improving performance while simplifying the interconnect structure by removing the intermediate solder material

Inventive Principle:

Principle #2Taking out (Extraction)

4Strength

If glass carrier wafer is used, then mechanical support is provided, but manufacturing complexity and cost increase

Engineering Contradiction:

Improvemechanical supportVSAvoidpackaging structure complexity

Core Design Contradiction:

StrengthVSDevice complexity

Solution Approach 1:

The carrier wafer is designed to perform multiple functions simultaneously: it provides mechanical support like a glass carrier, establishes electrical interconnects through integrated metal traces, and enables thermal management. This multi-functionality eliminates the need for separate glass carrier components, reducing complexity while maintaining mechanical strength

Inventive Principle:

Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves heat dissipation and electrical performance, reduces manufacturing costs, and eliminates the need for a glass carrier wafer, resulting in a reliable and cost-efficient semiconductor device packaging solution.

Implementation Method 1

enhancing thermal conductivity and electrical interconnects

Methodology Applied

Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

electrical interconnects

Methodology Applied

Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS20250329545A1Chip-substrate composite semiconductor device

Publication Date: 2025.10.23 INFINEON TECH AUSTRIA AG

AI summary

A method of manufacturing a semiconductor device includes forming a plurality of patterns of metal structures in a dielectric inorganic substrate wafer. The metal structures are accommodated in recesses of the dielectric inorganic substrate wafer and at least partly connect through the dielectric inorganic substrate. The method further includes providing a semiconductor wafer comprising a front side and a backside, wherein a plurality of electrodes is disposed on the front side of the semiconductor wafer. The front side of the semiconductor wafer is bonded to the dielectric inorganic substrate wafer to form a composite wafer, wherein the plurality of patterns of metal structures is connected to the plurality of electrodes. The composite wafer is separated into composite chips.