Composite Contact Structure Deposition for Better Sidewall Coverage

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Solution Overview

Problem

The scaling down of semiconductor devices poses challenges in achieving improved quality, yield, performance, and reliability while reducing complexity, particularly in terms of contact structure design and fabrication.

Innovation Solution

A method for fabricating a semiconductor device with a composite contact structure, involving the formation of a first dielectric layer, an expanded hole, a conformally deposited adhesive layer, a conductive layer, and a conductive structure using chemical vapor deposition processes, with a post-treatment involving diborane pulses to enhance grain size and resistivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional fabrication methods are used for scaling down semiconductor devices, then manufacturing process remains simple, but sidewall coverage and conductive structure properties deteriorate

Engineering Contradiction:
Improvesidewall coverageVSAvoidfabrication process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The fabrication process is divided into multiple deposition cycles with distinct stages: initial deposition step, intermediate steps with diborane pulses, and final completion steps. Each cycle deposits a portion of the conductive layer, allowing controlled buildup of material with specific properties at different depths and locations, thereby achieving superior sidewall coverage through incremental construction rather than single-step deposition

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The deposition process employs periodic introduction of diborane pulses during the deposition cycles. These periodic treatments modify the conductive layer properties at specific intervals, enhancing sidewall coverage and controlling material deposition patterns. The cyclic nature of deposition followed by periodic diborane treatment creates optimized microstructure and adhesion properties

Inventive Principle:
Principle #19Periodic action

2Manufacturing precision

If deposition cycles are increased to improve sidewall coverage, then sidewall coverage improves, but manufacturing time and process complexity increase

Engineering Contradiction:
Improvesidewall coverageVSAvoidmanufacturing throughput
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The deposition cycles are designed to continuously build the conductive layer while periodically introducing diborane pulses that enhance material properties without stopping the overall deposition process. This continuous useful action ensures that each deposition cycle contributes to sidewall coverage improvement while the periodic treatments optimize material properties, achieving both high precision and maintained productivity

Inventive Principle:
Principle #20Continuity of useful action

Solution Approach 2:

The process employs parameter changes by varying deposition conditions and diborane pulse timing across different cycles. By adjusting deposition parameters and diborane introduction timing, the process optimizes sidewall coverage in each cycle while maintaining overall manufacturing efficiency, preventing excessive process time accumulation

Inventive Principle:
Principle #35Parameter changes

3Reliability

If post-treatment with diborane pulses is applied to improve grain size and resistivity, then conductive structure properties improve, but process complexity increases

Engineering Contradiction:
Improveconductive structure resistivityVSAvoidprocess steps
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The diborane pulse treatments are merged with the deposition cycles rather than being separate post-treatment steps. The diborane pulses are introduced during specific phases of the deposition process, combining the benefits of material deposition and property enhancement in a unified process flow, thereby improving resistivity and grain size without proportionally increasing overall process complexity

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

Diborane serves as an intermediary substance that modifies the conductive layer properties during deposition. The diborane pulses act as a mediator between the deposition process and the final material properties, enabling control over grain size and resistivity through chemical interaction during the deposition cycles, thereby achieving reliable conductive structures through a controlled chemical mechanism

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method improves sidewall coverage of the conductive layer and enhances the grain size and resistivity of the conductive structure, leading to improved performance and reliability of the semiconductor device.

Implementation Method 1

conformally forming an adhesive layer in the expanded hole by a first chemical vapor deposition process; conformally forming a first conductive layer on the adhesive layer by a second chemical vapor deposition process; forming a first conductive structure on the first conductive layer by a third chemical vapor deposition process

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Implementation Method 2

The post-treatment includes introducing diborane pulses to the first conductive layer

Methodology Applied
Scientific EffectPost-treatment with diborane pulses:

Data Source

PatentUS12338528B2Method for fabricating semiconductor device with deposition cycles of chemical vapor deposition process to form composite contact structure
Publication Date: 2025.06.24 NAN YA TECH
  • US12338528B2 patent drawing
  • US12338528B2 patent drawing
  • US12338528B2 patent drawing

AI summary

The present application discloses a method for fabricating a semiconductor device. The method includes forming a first dielectric layer on a substrate; forming an expanded hole in the first dielectric layer; conformally forming an adhesive layer in the expanded hole by a first chemical vapor deposition process; conformally forming a first conductive layer on the adhesive layer by a second chemical vapor deposition process; and forming a first conductive structure on the first conductive layer by a third chemical vapor deposition process. The adhesive layer, the first conductive layer, and the first conductive structure together configure a composite contact structure. The second chemical vapor deposition process includes an initial deposition step and subsequent deposition cycles repeated until the first conductive layer is formed to a predetermined thickness.