Composite Contact Via Structures for 3D Memory
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Solution Overview
Problem
Three-dimensional memory devices face issues with significant lateral undulation and large voids in contact via structures, which decrease structural integrity and can trap fluorine, leading to damage during annealing processes.
Innovation Solution
The implementation of composite contact via structures featuring a transition metal layer and a fluorine-doped filler material, such as a silicide of the transition metal element or aluminum oxide, to reduce voids and prevent fluorine outgassing, thereby enhancing structural integrity and preventing damage to device layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If conventional contact via structures are used in three-dimensional memory devices, then the manufacturing process is simpler, but significant lateral undulation and large voids form, decreasing structural integrity
Solution Approach 1:
The patent applies composite materials by combining a transition metal layer (such as tungsten) with a filler material (such as silicon oxide or silicon nitride) to form a composite contact via structure. This composite structure reduces lateral undulation and voids while maintaining structural integrity, resolving the contradiction between simplicity and strength by introducing a multi-material composition rather than a single material approach.
Solution Approach 2:
The contact via structure is segmented into distinct functional layers: a transition metal layer providing electrical conductivity and a filler material portion providing structural support. This segmentation allows each layer to optimize its specific function, with the metal layer handling conduction and the filler material preventing void formation and lateral undulation, thereby improving overall structural integrity.
2Reliability
If conventional contact via structures are used, then manufacturing is easier, but large voids form that can trap fluorine, leading to damage during annealing
Solution Approach 1:
The patent converts the potential harm of void formation by filling them with a specific filler material that prevents fluorine trapping. The filler material portion is specifically designed to be fluorine-free or have low fluorine content, transforming the harmful void space into a beneficial fluorine-barrier region, thus improving device reliability during annealing processes.
Solution Approach 2:
The patent changes the material parameters of the contact via structure by selecting specific materials with appropriate properties: the transition metal provides electrical conductivity while the filler material (such as silicon oxide or silicon nitride) provides structural integrity and fluorine resistance. This parameter optimization ensures reliable performance without compromising manufacturability.
3Manufacturing precision
If the contact via structure uses high fluorine content filler material, then void filling is effective, but fluorine outgassing occurs during annealing, causing damage to device layers
Solution Approach 1:
The patent applies local quality by ensuring that the filler material portion has specifically low or zero fluorine content, contrasting with conventional filler materials that may contain fluorine. This localized material property optimization prevents fluorine outgassing during annealing while maintaining effective void filling, thus resolving the contradiction between manufacturing precision and harmful effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The composite contact via structures effectively reduce voids and prevent fluorine outgassing, improving the structural integrity of three-dimensional memory devices and minimizing damage during annealing steps.
Implementation Method 1
a fluorine-doped filler material portion in contact with the transition metal layer, and including fluorine atoms at a first average atomic concentration in a range from 0.1 part per million to 100 parts per million
Implementation Method 2
forming an interconnection via structure in the interconnection via cavity, wherein the interconnection via structure comprises: a transition metal layer composed primarily of a transition metal element
Data Source
AI summary
A semiconductor structure includes at least one first semiconductor device located on a substrate, lower-level dielectric material layers embedding lower-level metal interconnect structures, at least one second semiconductor device and a dielectric material portion that overlie the lower-level dielectric material layers, at least one upper-level dielectric material layer, and an interconnection via structure vertically extending from the at least one upper-level dielectric material layer to a conductive structure that can be a node of the at least one first semiconductor device or one of lower-level metal interconnect structures. The interconnection via structure includes a transition metal layer and a fluorine-doped filler material portion in contact with the transition metal layer, composed primarily of a filler material selected from a silicide of the transition metal element or aluminum oxide, and including fluorine atoms.