Composite CTE Ring Structure for Warpage-Resistant Semiconductor Packaging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in the semiconductor industry is the limitation of bonding integrated circuit chips directly onto substrates due to increased density and thermal stresses, leading to warping and delamination issues in 2D and 3D packages.
Innovation Solution
The integration of a ring structure with a first and second materials with a specific CTE and thermal expansion (CTE) that are embedded in the ring, which is embedded in the corners of the ring, which optimizes the total thermal expansion (CTE) of the ring by adjusting the shape, volume, and positions of the second material, and positions of the second material, optimizing the total thermal expansion (CTE) of the ring to minimize thermal stress within the integrated circuit package, thereby reducing the risk of warping and reducing thermal stresses at the interfaces, resulting in improved package reliability by minimizing thermal stresses and the risk of warping and delamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If integrated circuit chips are bonded directly onto substrates to achieve compact packaging, then packaging density is improved, but thermal stresses increase causing warping and delamination
Solution Approach 1:
An interposer is introduced as an intermediary component between the integrated circuit chip and the substrate. The interposer has a different coefficient of thermal expansion (CTE) than both the chip and substrate, serving as a thermal expansion buffer that reduces thermal stresses at the interfaces during temperature cycling, thereby preventing warping and delamination while enabling compact packaging.
Solution Approach 2:
The package structure employs composite materials with different thermal expansion properties - the interposer is made of a material that is neither too high nor too low in CTE compared to the chip and substrate. This composite approach creates a gradient structure that manages thermal stress distribution across the package, maintaining reliability while achieving high packaging density.
2Quantity of substance
If 3D packaging is implemented to increase integration density, then component density is improved, but thermal stress and warping risks increase
Solution Approach 1:
The interposer acts as a mediator in 3D packaging structures, providing thermal expansion management between vertically stacked components. By positioning the interposer between chips and substrates in 3D configurations, thermal stresses are distributed more evenly through the vertical stack, reducing warping risks while maintaining high integration density.
3Quantity of substance
If minimum feature size is reduced to increase integration density, then component density is improved, but bonding capability deteriorates
Solution Approach 1:
The interposer serves as a bonding intermediary that decouples the bonding requirements from the minimum feature size constraints. By bonding components to the interposer rather than directly to each other, the design allows for larger, more reliable bond interfaces even as feature sizes on the chips themselves continue to shrink, thereby maintaining bonding reliability while achieving high integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces thermal stresses and warping, enhancing the reliability of semiconductor packages by optimizing the thermal expansion properties of the ring structure, thus minimizing the risk of cracks and delamination.
Implementation Method 1
The ring may comprise a first portion that includes a first material having a first co-efficient of thermal expansion (CTE). The ring may also comprise second portions that include a second material having a second co-efficient of thermal expansion (CTE), wherein the second CTE is lower than the first CTE.
Data Source
AI summary
A method includes forming a redistribution structure over a carrier, attaching a semiconductor die to the redistribution structure using first conductive connectors, dispensing a first underfill into a first gap between the semiconductor die and the redistribution structure, bonding a substrate to the redistribution structure using second conductive connectors, the substrate being bonded to an opposing side of the redistribution structure as the semiconductor die, and attaching a ring to the substrate, where the ring surrounds the semiconductor die and the first underfill, and where the ring includes a first portion that includes a first material having a first co-efficient of thermal expansion, and second portions that include a second material having a second co-efficient of thermal expansion that is different from the first co-efficient of thermal expansion.