Composite Device Merging Depletion FET and Bipolar Transistor
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Solution Overview
Problem
Conventional RF power amplifiers require high primary voltages, which can lead to low voltage breakdown in transistors used for digital waveform modulation, necessitating separate circuits for signal and RF power generation due to impedance mismatches and voltage standing wave ratio (VSWR) issues.
Innovation Solution
A composite device combining a depletion mode FET with a bipolar transistor or NMOS transistor, where the collector and source terminals are directly connected, and the emitter and gate terminals are connected to bias the FET, allowing for low voltage operation while supporting higher voltages, and optionally using gallium nitride or silicon germanium transistors for enhanced performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If high primary voltage is used for RF power generation, then RF power efficiency is improved, but transistor breakdown risk increases
Solution Approach 1:
The patent combines a high-voltage depletion mode FET with a low-voltage bipolar transistor in a cascode configuration to create a single composite device. The FET handles high-voltage RF power amplification while the bipolar transistor provides low-voltage digital waveform modulation, eliminating the need for separate circuits and protecting the modulation transistor from high-voltage breakdown.
Solution Approach 2:
The composite device segments the voltage handling functions: the depletion mode FET is responsible for high-voltage RF power generation, while the bipolar transistor handles low-voltage digital signaling. This segmentation allows each component to operate within its optimal voltage range, preventing breakdown while maintaining efficiency.
2Reliability
If separate circuits are used for signal waveform generation and RF power generation, then voltage breakdown protection is improved, but device complexity increases
Solution Approach 1:
The patent merges the signal waveform generation circuit and RF power amplification circuit into a single composite device. The cascode configuration integrates the low-voltage bipolar transistor (for digital modulation) and high-voltage depletion mode FET (for RF power amplification) into one unified structure, reducing component count and interconnection complexity while maintaining voltage isolation.
3Reliability
If impedance mismatch protection is implemented, then transistor reliability is improved, but circuit complexity increases
Solution Approach 1:
The cascode configuration provides inherent protection against impedance mismatch and VSWR effects. The high-voltage FET's drain terminal naturally handles voltage reflections and standing waves without requiring additional protection circuits, as the device structure itself provides the necessary voltage isolation and protection for the low-voltage bipolar transistor.
Data Source
AI summary
A composite device includes a depletion mode FET coupled to a bipolar transistor. The FET includes gate, drain and source terminals, and the bipolar transistor includes base, collector and emitter terminals. The collector terminal of the bipolar transistor and the source terminal of the depletion mode FET are directly connected to each other. Additionally, the emitter terminal of the bipolar transistor and the gate terminal of the depletion mode FET are directly connected to each other. The voltage between the collector and emitter terminals, VCE, is configured to bias the depletion mode FET. The VCE voltage has a value that is equal and opposite to a voltage VGS between the gate and source terminals of the depletion mode FET.