Composite Dielectric Region for Low Loss IPD Substrates
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Solution Overview
Problem
Integrated passive devices (IPDs) on semiconductor substrates suffer from significant electro-magnetic coupling losses and area bloat due to adverse interactions with active devices, leading to degraded performance and increased manufacturing costs.
Innovation Solution
The use of a composite dielectric region with electrically floating poly-crystalline or amorphous inclusions separated by dielectric portions underlying IPDs, which reduces electro-magnetic coupling and mechanical stress, allowing for closer placement of IPDs to active devices without adverse effects on manufacturing yield or circuit performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If IPDs are formed on the same substrate as active devices, then manufacturing efficiency is improved, but electro-magnetic coupling losses increase
Solution Approach 1:
A dielectric layer is introduced as an intermediary between the IPDs and the semiconductor substrate. This dielectric layer acts as a mediator that reduces the electro-magnetic coupling between the IPDs and the conductive substrate, thereby reducing eddy current losses while allowing the IPDs to remain on the same substrate for manufacturing efficiency.
Solution Approach 2:
The electrical properties of the substrate interface are changed by introducing a dielectric material with different permittivity and conductivity characteristics. This parameter change reduces the electro-magnetic coupling coefficient between the IPDs and the substrate, minimizing energy losses while maintaining the integrated structure.
2Area of stationary object
If IPDs are placed closer to active devices, then area is reduced, but coupling losses increase
Solution Approach 1:
The dielectric layer serves as a protective intermediary that enables closer placement of IPDs to active devices. By reducing the electro-magnetic coupling through this dielectric barrier, the design allows minimized inter-element spacing without suffering from increased coupling losses, thus reducing overall chip area.
3Ease of manufacture
If IPDs are integrated on the substrate, then manufacturing cost is reduced, but mechanical stress increases
Solution Approach 1:
The thermal expansion coefficient mismatch between different materials is addressed by introducing a dielectric layer with intermediate thermal properties. This parameter matching reduces the mechanical stress generated during thermal processing cycles, enabling cost-effective integration without compromising device reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes electro-magnetic coupling losses, improves circuit efficiency, reduces substrate stress, and allows for increased IPD placement density without area bloat, enhancing manufacturing yield and overall circuit performance.
Implementation Method 1
Electro-magnetic (E-M) coupling of IPDs to the semiconductor substrates on which they are formed can give rise to eddy current losses in the substrate
Implementation Method 2
Electro-magnetic (E-M) coupling of IPDs to the semiconductor substrates on which they are formed can give rise to eddy current losses in the substrate
Implementation Method 3
a first substrate of a first material having a first thermal expansion coefficient and having a first surface
Data Source
AI summary
Electronic elements having an active device region and integrated passive device (IPD) region on a common substrate preferably include a composite dielectric region in the IPD region underlying the IPD to reduce electro-magnetic (E-M) coupling to the substrate. Mechanical stress created by plain dielectric regions and its deleterious affect on performance, manufacturing yield and occupied area may be avoided by providing electrically isolated inclusions in the composite dielectric region of a material having a thermal expansion coefficient (TEC) less than that of the dielectric material in the composite dielectric region. For silicon substrates, non-single crystal silicon is suitable for the inclusions and silicon oxide for the dielectric material. The inclusions preferably have a blade-like shape separated by and enclosed within the dielectric material.