Composite DRAM Capacitor Structure for High Capacitance Scaling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuit devices face challenges in maintaining desired capacitance due to spatial limitations and design rule constraints as they undergo high integration and miniaturization, particularly in capacitors within dynamic random access memory (DRAM) where the area of a unit cell is reduced.
Innovation Solution
An integrated circuit device is designed with a capacitor structure that includes a dielectric film composite comprising an anti-ferroelectric material, ferroelectric material, and paraelectric material, where the paraelectric material is distributed at the grain boundary between anti-ferroelectric and ferroelectric grains, forming a nano-size 3D structure to enhance capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the area of a unit cell is reduced to increase integration density, then the integration degree is improved, but the capacitance of the capacitor deteriorates
Solution Approach 1:
The patent employs a composite dielectric film structure comprising multiple dielectric layers with different materials (first dielectric layer, second dielectric layer, third dielectric layer) having different dielectric constants. This composite structure enables the capacitor to achieve high capacitance in a reduced area by combining the advantages of different dielectric materials, where at least one layer has a dielectric constant of 10 or more, thereby resolving the contradiction between miniaturization and capacitance maintenance.
Solution Approach 2:
The patent changes the dielectric parameters by selecting materials with specific dielectric constants (at least one layer with dielectric constant ≥10) and controlling the thickness of each dielectric layer. By optimizing the combination of dielectric constants and layer thicknesses, the capacitor achieves desired capacitance values despite the reduced unit cell area, directly addressing the contradiction between integration density and capacitance.
2Area of stationary object
If the capacitor area is reduced to fit high integration requirements, then the device complexity is reduced, but the manufacturing precision required to maintain capacitance increases
Solution Approach 1:
The multi-layer composite dielectric structure provides manufacturing robustness by distributing the capacitance requirement across multiple layers. This allows for better process control and tolerance accumulation, where variations in individual layer thicknesses can be compensated by the combined effect of multiple layers, thereby reducing the stringent precision requirements compared to a single thin-layer structure.
Solution Approach 2:
The patent transitions from a single-layer to a multi-layer vertical structure, utilizing the thickness dimension to achieve high capacitance. This vertical stacking approach converts the area reduction problem into a thickness optimization problem, where precise control of multiple thinner layers is more manufacturable than controlling a single ultra-thin layer, thus reducing manufacturing precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for a relatively high capacitance to be maintained efficiently, even in reduced spatial areas, by leveraging the phase interaction between different dielectric materials and minimizing size effects, thus addressing the capacitance requirements in high-integration integrated circuit devices.
Implementation Method 1
a first dielectric film including an anti-ferroelectric material
Implementation Method 2
a second dielectric filler including a ferroelectric material
Implementation Method 3
a third dielectric filler including a paraelectric material
Implementation Method 4
the dielectric film composite includes a first dielectric film including an anti-ferroelectric material, a second dielectric filler distributed and disposed in the first dielectric film, the second dielectric filler including a ferroelectric material, and a third dielectric filler distributed and disposed in the first dielectric film
Data Source
AI summary
An integrated circuit device includes a transistor disposed on a substrate and a capacitor structure electrically connected with the transistor, wherein the capacitor structure includes a first electrode, a dielectric film composite disposed on the first electrode, and a second electrode disposed on the dielectric film composite, and the dielectric film composite includes a first dielectric film including an anti-ferroelectric material, a second dielectric filler distributed and disposed in the first dielectric film, the second dielectric filler including a ferroelectric material, and a third dielectric filler distributed and disposed in the first dielectric film, the third dielectric filler including a paraelectric material and having an average diameter which is less than an average diameter of the second dielectric filler.