Composite Dummy Fin Structure for Leakage Isolation in FinFETs
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Solution Overview
Problem
Dummy fins in semiconductor devices can form voids that lead to leakage paths, reducing electrical isolation and device performance, and may suffer from bending issues causing AC performance degradation.
Innovation Solution
A dummy fin configuration with a low-k dielectric material outer shell and a high-k dielectric material inner core is used to fill voids, preventing leakage paths and enhancing electrical isolation, while being compatible with finFET formation processes to minimize processing issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dummy fin is formed in semiconductor devices, then electrical isolation between active fins is improved, but voids form in the dummy fin leading to leakage paths that reduce isolation effectiveness
Solution Approach 1:
The patent changes the material parameter of the dummy fin by filling voids with conductive material (such as metal) to transform the dummy fin from a simple dielectric structure to a composite structure with controlled electrical properties. This parameter change allows the dummy fin to maintain electrical isolation functionality while preventing leakage paths through the voids.
Solution Approach 2:
The patent creates a composite dummy fin structure combining dielectric material with conductive material filling. This composite approach allows the dummy fin to simultaneously provide mechanical support, electrical isolation where needed, and void prevention, resolving the contradiction between isolation effectiveness and void formation.
2Reliability
If a dummy fin is formed to provide electrical isolation, then device performance is improved, but bending issues occur causing AC performance degradation
Solution Approach 1:
The composite dummy fin structure with conductive material filling provides enhanced mechanical stability and resistance to bending. The combined structure has improved structural integrity compared to a simple dielectric dummy fin, reducing bending issues and associated AC performance degradation.
Solution Approach 2:
By changing the material composition and physical properties of the dummy fin through conductive material filling, the structural parameters such as rigidity and stability are improved, thereby reducing bending deformation and maintaining AC performance.
3Ease of manufacture
If voids are left in the dummy fin structure, then manufacturing process is simplified, but leakage paths form that reduce electrical isolation
Solution Approach 1:
The conductive material filling is performed as a preliminary action during the manufacturing process, before final device assembly. This preliminary filling of voids prevents future leakage path formation while maintaining manufacturing efficiency, as the filling process is integrated into the existing fabrication sequence.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed dummy fin design effectively increases electrical isolation and semiconductor device performance by blocking leakage paths and avoiding AC performance degradation, while being easily integrated into existing finFET processes.
Implementation Method 1
A dummy fin configuration with a low-k dielectric material outer shell and a high-k dielectric material inner core is used to fill voids, preventing leakage paths and enhancing electrical isolation
Data Source
AI summary
A dummy fin described herein includes a low dielectric constant (low-k or LK) material outer shell. A leakage path that would otherwise occur due to a void being formed in the low-k material outer shell is filled with a high dielectric constant (high-k or HK) material inner core. This increases the effectiveness of the dummy fin to provide electrical isolation and increases device performance of a semiconductor device in which the dummy fin is included. Moreover, the dummy fin described herein may not suffer from bending issues experienced in other types of dummy fins, which may otherwise cause high-k induced alternating current (AC) performance degradation. The processes for forming the dummy fins described herein are compatible with other fin field effect transistor (finFET) formation processes and are be easily integrated to minimize and/or prevent polishing issues, etch back issues, and/or other types of semiconductor processing issues.