Composite Etch Stop Layer for MMIC Dielectric Loading

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Solution Overview

Problem

The existing methods for forming monolithic microwave integrated circuits (MMICs) face challenges in minimizing dielectric loading effects at higher frequencies, particularly due to the deposition of silicon nitride passivation layers which adversely impact device performance, and the etch stop layers are susceptible to damage from common fabrication chemicals like ammonia and photoresist developers.

Innovation Solution

A composite etch stop layer structure is formed comprising a first etch stop layer, a buffer layer, and a second etch stop layer, where the buffer layer protects the first etch stop layer from photolithographic processing chemicals, and the second etch stop layer is selectively removable using ammonia, thereby mitigating the impact on RF performance and allowing precise etching without damaging the underlying layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If PECVD silicon nitride is deposited as a passivation layer, then device passivation and capacitor dielectric functions are achieved, but dielectric loading effects increase and RF performance deteriorates at higher frequencies

Engineering Contradiction:
Improvedevice passivationVSAvoiddielectric loading effects
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent segments the etch stop layer into a composite structure with multiple functional layers (first etch stop layer, buffer layer, second etch stop layer), each serving specific purposes. The buffer layer specifically protects against dielectric loading by being selectively removable, allowing precise control over where dielectric material is deposited and retained.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The composite etch stop layer structure provides local quality differentiation through its layered design. The buffer layer is strategically positioned to protect specific regions from dielectric deposition, while other layers provide etch stopping functions. This allows different regions of the device to have different dielectric loading characteristics optimized for their specific functions.

Inventive Principle:
Principle #3Local quality

2Ease of manufacture

If a single etch stop layer is used, then the structure is simple and manufacturing is easier, but the layer is susceptible to damage from photolithographic chemicals like ammonia and photoresist developer

Engineering Contradiction:
Improveetch stop layer fabricationVSAvoidetch stop layer integrity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent employs a composite etch stop layer structure consisting of multiple materials with different chemical resistances. The buffer layer is specifically designed to resist photolithographic chemicals (ammonia, photoresist developer), while the first and second etch stop layers provide the necessary etch stopping functionality. This composite approach maintains manufacturing simplicity while significantly improving chemical resistance and layer integrity.

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The buffer layer acts as an intermediary protective layer between the photolithographic chemicals and the etch stop layers. It specifically resists damage from ammonia and photoresist developer, thereby protecting the underlying etch stop layer structure during fabrication processes while allowing the etch stop function to remain effective.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Manufacturing precision

If chemicals are used to remove residual etch stop material, then clean surfaces are achieved for subsequent processing, but the etch stop layer is damaged or compromised during the process

Engineering Contradiction:
Improvesurface cleanlinessVSAvoidetch stop layer protection
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent utilizes parameter changes in the form of selective chemical etching. Different layers in the composite etch stop structure have different etch rates and chemical resistances. The buffer layer can be selectively removed by timed exposure to ammonia, while the first and second etch stop layers remain intact. This allows precise control over which layers are removed and which are retained, achieving clean surfaces without compromising the protective etch stop functionality.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively minimizes the impact of dielectric loading on MMICs by protecting the etch stop layers during fabrication, ensuring reliable performance at higher frequencies and allowing for precise etching without compromising the integrity of the semiconductor structure.

Implementation Method 1

chemicals used in the photolithographic processing while effecting the second etch stop layer are prevented from effecting the first etch stop layer by the buffer layer

Methodology Applied
Scientific EffectChemical resistance:

Implementation Method 2

ammonia acts as a highly selective etchant to Atomic Layer Deposition ( ALD) deposited aluminum oxide to PECVD nitride

Methodology Applied
Scientific EffectSelective etching:

Implementation Method 3

the effects of dielectric loading on various MMIC conduction paths (including gates and transmission lines) becomes more pronounced. The minimization of such loading is critical to achieving the desired gain performance

Methodology Applied
Scientific EffectDielectric loading minimization: Dielectric Permittivity

Data Source

PatentEP3281229B1Monolithic integrated circuit (MMIC) structure having composite etch stop layer and method for forming such structure
Publication Date: 2022.06.15 RAYTHEON CO
  • EP3281229B1 patent drawingFigure 1A~1B
  • EP3281229B1 patent drawingFigure 1C~1C`
  • EP3281229B1 patent drawingFigure 1D

AI summary

A method for forming a semiconductor structure having a transistor device with a control electrode (20) for controlling a flow of carriers between a first electrode (16) and a second electrode (18) includes a passivation layer (24) with an etch stop layer (26) deposited on the passivation layer. The etch stop layer includes a first etch stop layer (26a) on the passivation layer, a buffer layer (26b) on the first etch stop layer, and a second etch stop layer (26c) on the buffer layer and a dielectric layer (40) formed over the etch stop layer. A window is etched through a selected region in the dielectric layer over the control electrode, to expose a portion of the etch stop layer. A metal layer (34a) is formed on a portion of the etch stop layer and a second metal layer (56a) is deposited on the portion of the dielectric layer formed on the first mentioned metal layer.