Composite Etch Stop Layer for Precise Via Hole Landing
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Solution Overview
Problem
Traditional silicon-based etch stop layers are inadequate in preventing via hole over-etching and under-etching issues in advanced semiconductor manufacturing processes due to wider conductor line widths and higher aspect ratios, leading to defects such as open circuits.
Innovation Solution
Employing a silicon-containing dielectric (SCD) layer and a metal-containing dielectric (MCD) layer as an etch stop layer, which provides enhanced etch selectivity and prevents over-etching and under-etching by ensuring all via holes land accurately, using processes like PVD, CVD, and ALD for deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a traditional silicon-based etch stop layer is used, then the structure is simple and manufacturing is easy, but it cannot effectively prevent via hole over-etching and under-etching in advanced processes
Solution Approach 1:
The patent applies composite materials by combining multiple dielectric layers with different etch selectivities. Specifically, it uses a first dielectric layer (e.g., silicon oxide) and a second dielectric layer (e.g., silicon nitride or carbon-doped silicon oxide) with distinct etching characteristics. This composite structure provides enhanced etch selectivity compared to traditional single-layer silicon-based etch stop layers, enabling precise control of via hole etching depth and preventing both over-etching and under-etching in advanced semiconductor processes.
2Adaptability or versatility
If conductor line widths are increased and via aspect ratios are increased, then device design flexibility improves, but etch selectivity deteriorates leading to via hole defects
Solution Approach 1:
The patent applies parameter changes by modifying the etch selectivity parameters through material composition adjustments. The first and second dielectric layers are engineered with different etch selectivity ratios relative to the low-k dielectric layer. This allows the etch process to accommodate varying conductor line widths and via aspect ratios while maintaining precise etching control, preventing via hole defects even when design parameters are adjusted for device flexibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The new etch stop layer effectively prevents via hole defects, ensuring precise etching and reducing package size by maintaining etch selectivity and hermeticity, thus improving semiconductor device integrity.
Implementation Method 1
processes like PVD, CVD, and ALD for deposition
Implementation Method 2
processes like PVD, CVD, and ALD for deposition
Implementation Method 3
processes like PVD, CVD, and ALD for deposition
Data Source
AI summary
A semiconductor device includes a substrate, a first conductive feature over a portion of the substrate, and an etch stop layer over the substrate and the first conductive feature. The etch stop layer includes a silicon-containing dielectric (SCD) layer and a metal-containing dielectric (MCD) layer over the SCD layer. The semiconductor device further includes a dielectric layer over the etch stop layer, and a second conductive feature in the dielectric layer. The second conductive feature penetrates the etch stop layer and electrically connects to the first conductive feature.