Composite Gate Dielectric Structure for Lower MOSFET Leakage
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Solution Overview
Problem
As transistors scale down, reducing high-k dielectric material thickness in gate stacks leads to increased leakage current due to insufficient charge barrier heights and capacitance equivalent thickness scaling limitations, which affects the performance and reliability of integrated circuits.
Innovation Solution
Incorporating a rare earth element, such as yttrium, into the gate dielectric layer, combined with a group 4 element and oxygen, to form a high-k dielectric layer with a multilayer structure, which enhances the conduction band offset and dielectric constant, reducing leakage current and enabling further CET scaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high-k dielectric material thickness is reduced to improve MOSFET performance, then capacitance equivalent thickness scaling is improved, but leakage current increases
Solution Approach 1:
The patent employs a composite gate dielectric structure consisting of multiple layers with different dielectric materials. The first gate dielectric layer has a first dielectric constant and the second gate dielectric layer has a second dielectric constant, creating a composite structure that optimizes both capacitance and leakage characteristics. This composite approach allows achieving lower effective CET while maintaining adequate charge barrier height to suppress leakage current.
Solution Approach 2:
The patent applies different dielectric materials with specific properties to different regions of the gate stack. By positioning layers with different dielectric constants at specific locations, the structure achieves local optimization where the first layer addresses one aspect of the contradiction while the second layer addresses the other, enabling fine-tuned control over both performance and leakage.
2Productivity
If device dimensions are scaled down to improve production efficiency, then production cost is reduced, but manufacturing process complexity increases
Solution Approach 1:
The gate dielectric is segmented into multiple distinct layers, each with specific thickness and dielectric constant requirements. This segmentation allows independent optimization of each layer's properties and enables the structure to meet stringent scaling requirements while maintaining manufacturability through standardized deposition processes for each layer.
3Ease of manufacture
If conventional high-k dielectric structures are used in scaled devices, then manufacturing is simplified, but charge barrier height becomes insufficient leading to increased leakage
Solution Approach 1:
The patent uses composite dielectric materials in a multi-layer configuration where each layer contributes specific properties. The combination of materials with different dielectric constants creates an effective charge barrier that is sufficient for scaled devices while still using established deposition and fabrication techniques, thus maintaining ease of manufacture.
Solution Approach 2:
The patent modifies key parameters of the gate dielectric structure, specifically the dielectric constant distribution across layers and the thickness of each layer. By carefully selecting and adjusting these parameters, the structure achieves adequate charge barrier height for reliability while remaining compatible with existing manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces electron tunneling probability and leakage current while maintaining or improving device reliability and performance by increasing the dielectric constant of the gate dielectric, allowing for continued scaling of integrated circuits without increasing physical thickness.
Implementation Method 1
reduces electron tunneling probability and leakage current
Implementation Method 2
increases the dielectric constant of the gate dielectric
Data Source
AI summary
Gate stack fabrication techniques are disclosed for capacitance equivalent thickness scaling. An exemplary method for forming a gate stack includes forming an interfacial layer, forming a high-k dielectric layer over the interfacial layer, and forming an electrically conductive gate layer over the high-k dielectric layer. Forming the high-k dielectric layer includes forming a group 4 element-containing dielectric layer (e.g., an HfO2 layer and/or a ZrO2 layer) and forming a rare earth element-containing dielectric layer. In some embodiments, the rare earth element-containing dielectric layer includes yttrium and oxygen, nitrogen, carbon, or a combination thereof. The electrically conductive gate layer is formed over the rare earth element-containing dielectric layer (i.e., the rare earth element-containing dielectric layer is not removed and remains in the gate stack). The rare earth element-containing dielectric layer can be formed before, after, or between forming sublayers of group 4 element-containing dielectric layer.