Composite Gate Electrode for Distinct Threshold Voltages
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Solution Overview
Problem
Existing methods for forming PMOS and NMOS semiconductor devices with different threshold voltages are complex and cumbersome, requiring selective etching and planarization of multiple gate electrode layers.
Innovation Solution
A semiconductor device and method where a composite gate electrode is formed with one conductive material stacking on another on a substrate, using a silicide layer to achieve different threshold voltages by leveraging the work function difference between the silicide and a lower electrode layer, eliminating the need for selective etching and planarization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If selective etching and planarization are performed to form different gate electrode layers, then different threshold voltages for PMOS and NMOS are achieved, but the fabrication process becomes complex and troublesome
Solution Approach 1:
The gate electrode is segmented into two distinct layers: a first gate electrode layer formed entirely over the substrate, and a second gate electrode layer formed selectively in regions where the first layer is removed. This segmentation allows different materials to be used in different regions to achieve different threshold voltages for PMOS and NMOS devices.
Solution Approach 2:
Instead of forming different gate electrode layers directly through selective deposition, the invention inverts the approach by first forming a complete first gate electrode layer, then selectively removing portions of it to create regions for the second gate electrode layer. This inversion simplifies the overall process by using a single initial deposition step followed by selective removal rather than multiple selective deposition steps.
2Reliability
If multiple gate electrode layers are formed separately, then different work functions are achieved for different threshold voltages, but the process requires multiple deposition and planarization steps
Solution Approach 1:
The first gate electrode layer is formed in advance over the entire substrate before any selective removal or second layer deposition. This preliminary action establishes a uniform base layer that simplifies subsequent processing steps and ensures consistent coverage across all device regions.
Solution Approach 2:
The invention merges the formation of different gate electrode layers into a unified process sequence where the first gate electrode layer serves as a common base for both PMOS and NMOS regions, with selective removal creating the differentiation. This merging reduces the total number of separate deposition and planarization steps required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the process of forming PMOS and NMOS devices with distinct threshold voltages by using a single silicide layer to control the threshold voltage, reducing complexity and improving manufacturing efficiency.
Implementation Method 1
leveraging the work function difference between the silicide and a lower electrode layer
Data Source
AI summary
A semiconductor device includes a first gate structure including a gate dielectric layer directly contacting the substrate, a bottom electrode on the gate dielectric layer and a top electrode on the bottom electrode, and a second gate structure including a gate dielectric layer directly contacting the substrate and a gate electrode on the gate dielectric layer.