Composite Gate Oxide Radiation Hardness via Segmentation
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Solution Overview
Problem
Cosmic radiation, such as gamma rays, affects semiconductor devices in space by creating electron/hole pairs, where holes can become trapped in oxide layers, leading to performance degradation and mode conversion of transistors, causing off-state leakage and threshold voltage shifts, rendering devices unreliable in harsh radiation environments.
Innovation Solution
Creating defect sites in insulator layers to trap holes, forming a composite thick gate oxide layer using CVD processes, which includes a thin thermal oxide and deposited spacer materials, improving radiation hardness with minimal perturbation to existing semiconductor fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick gate oxide layer is formed to improve radiation hardness, then device reliability in radiation environments improves, but manufacturing complexity and process perturbation increase
Solution Approach 1:
The gate oxide layer is segmented into multiple portions: a first portion formed by thermal oxidation and a second portion formed by CVD. This segmentation allows each portion to contribute different properties - the thermal oxide provides good interface quality while the CVD oxide adds thickness for radiation hardness, achieving the desired reliability without requiring a completely new thick oxide process
Solution Approach 2:
The gate oxide is formed as a composite structure combining thermally grown oxide and CVD-deposited oxide. This composite approach leverages the advantages of both formation methods - the thermal oxide's excellent silicon interface and the CVD oxide's controllable thickness and radiation hardness - to achieve reliable radiation-hardened devices
2Reliability
If defect sites are created in insulator layers to trap holes, then threshold voltage control improves, but manufacturing precision requirements increase
Solution Approach 1:
Defect sites are preliminarily created in the insulator layer during the CVD process by controlling deposition conditions to form nitrogen-containing defects. These pre-formed defect sites are positioned to trap holes before they can migrate to critical regions, thereby controlling threshold voltage without requiring precise post-processing adjustment of defect locations
Solution Approach 2:
The patent converts the potentially harmful effect of holes trapped in oxide layers (which causes threshold voltage shifts) into a beneficial control mechanism. By deliberately creating defect sites that trap holes in controlled locations, the invention transforms an uncontrolled harmful effect into a controlled feature that stabilizes threshold voltage
3Reliability
If CVD processes are used to form insulator layers, then radiation hardness improves, but manufacturing process complexity increases
Solution Approach 1:
The patent merges the CVD process with existing thermal oxidation steps in a unified gate oxide formation sequence. The CVD oxide deposition is integrated into the standard gate oxide fabrication flow, combining it with thermal oxidation to create a multi-layer structure that achieves radiation hardness while maintaining compatibility with existing manufacturing processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively controls threshold voltage and other parameters, enhancing the reliability of semiconductor devices in radiation-hardened environments by trapping holes and maintaining device performance, reducing the risk of mode conversion and leakage.
Implementation Method 1
a second portion is formed by depositing a spacer material on the thin gate insulator layer
Implementation Method 2
a first portion is a thin gate insulator layer formed by a thermal method
Data Source
AI summary
An electronic system, method of manufacture of a semiconductor structure, and one or more semiconductor structures are disclosed. For example, a method of manufacture of a semiconductor structure is disclosed, which includes forming a first semiconductor substructure over a semiconductor substrate, forming a first spacer layer over the first semiconductor substructure and the semiconductor substrate, and forming a second semiconductor substructure over at least a portion of the first spacer layer.