Composite Gate Spacer Layout for Lower Overlap Capacitance
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Solution Overview
Problem
Current semiconductor fabrication techniques face challenges in controlling overlap capacitance between the gate structure and source/drain region due to materials with high dielectric constants, affecting device performance.
Innovation Solution
A method involving the formation of a gate structure, a contact etch stop layer, and an interlayer dielectric layer, followed by a curing process using ozone and thermal treatment to alter the dielectric constants, and a replacement metal gate process to transform the gate structure into a metal gate, thereby reducing overlap capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If materials with high dielectric constant are used for spacer and contact etch stop layer, then the gate structure can be formed with good structural integrity, but the overlap capacitance between gate structure and source/drain region increases
Solution Approach 1:
The patent applies local quality by creating a composite spacer structure with different dielectric constant regions. The first spacer portion has a higher dielectric constant than the second spacer portion, allowing different regions of the same component to have different electrical properties. This enables the spacer to maintain structural integrity where needed while reducing overlap capacitance in critical regions, thus resolving the contradiction between structural strength and capacitance control.
2Ease of manufacture
If conventional polysilicon gate is used, then the fabrication process is simple, but the device performance deteriorates due to boron penetration and depletion effect
Solution Approach 1:
The patent implements parameter changes by transitioning from conventional polysilicon gate to a metal gate structure with high-k dielectric layer. This changes the fundamental electrical parameters of the gate, eliminating boron penetration and depletion effects that plague polysilicon gates. The metal gate with high-k dielectric provides better gate control and higher gate capacitance, significantly improving device performance while maintaining fabrication compatibility through the described process steps.
3Manufacturing precision
If the dielectric constant of spacer and contact etch stop layer is increased, then the gate structure can be formed with better control, but the overlap capacitance cannot be controlled under desirable range
Solution Approach 1:
The patent applies segmentation by dividing the spacer into two distinct portions with different dielectric constants. The first spacer portion (adjacent to gate structure) has higher dielectric constant for better gate control, while the second spacer portion (extending toward source/drain) has lower dielectric constant to reduce overlap capacitance. This segmented approach allows independent optimization of each region's electrical characteristics, resolving the contradiction between gate control precision and capacitance management.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively lowers overlap capacitance and improves device performance by adjusting the dielectric constants of the spacer and interlayer dielectric layers, enhancing the control over the gate structure and source/drain region.
Implementation Method 1
performing a curing process so that an oxygen concentration of the CESL is different from the oxygen concentration of the ILD layer
Data Source
AI summary
A semiconductor device includes a gate structure on a substrate, an offset spacer adjacent to the gate structure, a main spacer around the offset spacer, a source/drain region adjacent to two sides of the main spacer, a contact etch stop layer (CESL) adjacent to the main spacer, and an interlayer dielectric (ILD) layer around the CESL. Preferably, a dielectric constant of the offset spacer is higher than a dielectric constant of the main spacer.