Composite Impurity Source/Drain Lines for Low-Resistance Memory Arrays
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Solution Overview
Problem
As memory cell sizes decrease, buried diffusion lines in virtual ground arrays face challenges such as increased resistance, reduced programming speed, and data disturbance due to secondary electrons from neighboring cells, which degrade memory performance.
Innovation Solution
The implementation of composite impurity profiles in source/drain terminals with phosphorous for conductivity and carbon/nitrogen to suppress diffusion, along with arsenic for deep impurity profiles, creates high-conductivity, low-resistance bit lines that reduce neighbor cell disturbance and enhance programming efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the buried diffusion lines are made narrower to increase memory density, then the memory array density is improved, but the resistance of the lines becomes higher
Solution Approach 1:
The patent changes the doping concentration parameter by introducing a composite impurity profile with multiple doping levels. The first impurity provides high conductivity in the source/drain region, while the second impurity creates a steep doping profile that acts as a barrier. This parameter change enables narrow diffusion lines to maintain low resistance despite reduced dimensions.
Solution Approach 2:
The patent uses a composite impurity profile combining two different impurities with distinct properties. The first impurity (e.g., phosphorous) provides high carrier concentration for low resistance, while the second impurity (e.g., boron) creates a blocking barrier. This composite approach allows the diffusion line to simultaneously achieve low resistance and effective electron blocking in narrow geometries.
2Object-affected harmful factors
If deep impurities are provided in the buried diffusion lines to block secondary electrons, then neighbor cell disturbance is reduced, but the manufacturing complexity increases
Solution Approach 1:
The patent segments the impurity profile into distinct regions: a first impurity concentrated in the source/drain region for conductivity, and a second impurity creating a steep profile at the interface for electron blocking. This segmentation allows each impurity to perform its specific function independently, achieving effective electron blocking without excessive manufacturing complexity.
Solution Approach 2:
The patent applies different impurity concentrations and types at different locations within the diffusion line. The first impurity is concentrated where high conductivity is needed, while the second impurity is positioned at the channel interface where electron blocking is required. This local differentiation optimizes performance while managing manufacturing complexity.
3Quantity of substance
If the channel length and source/drain line width are reduced below 50 nanometers to increase density, then the memory array density is improved, but the memory performance degrades
Solution Approach 1:
The patent changes the electrical parameters of the source/drain lines by implementing a composite impurity profile. The first impurity provides high carrier concentration that compensates for the reduced cross-sectional area of narrow lines, maintaining low resistance and high programming speed despite sub-50nm dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables high-speed operation and improved endurance in dense memory arrays by maintaining low resistance and reducing data disturbance, even at critical dimensions below 50 nanometers, while supporting hot carrier programming.
Implementation Method 1
The source/drain lines have a first impurity which provides charge carriers having a carrier type, making the source/drain lines conductive. The first impurity can be phosphorous, which is characterized by low resistance and high diffusivity in silicon.
Implementation Method 2
A second impurity in interface regions between the channel regions and the source/drain lines suppresses diffusion of the first impurity into the channel regions. The second impurity, such as carbon, nitrogen or both, suppresses diffusion of phosphorous. It is believed the diffusion is suppressed by occupying or interacting with interstitial defects in the substrate.
Implementation Method 3
The source/drain lines can include a third impurity providing charge carriers of the same carrier type as the first impurity, such as the higher atomic mass arsenic complementing the lower atomic mass phosphorous. The third impurity can provide a steep impurity profile of low diffusivity dopant, adding depth to the source/drain line so that it can act as a barrier to charge carriers, such as secondary electrons.
Data Source
AI summary
An integrated circuit comprises a memory array including diffusion bit lines having composite impurity profiles in a substrate. A plurality of word lines overlies channel regions in the substrate between the diffusion bit lines, with data storage structures such as floating gate structures or dielectric charge trapping structures, at the cross-points. The composite impurity diffusion bit lines provide source/drain terminals on opposing sides of the channel regions that have high conductivity, good depth and steep doping profiles, even with channel region critical dimensions below 50 nanometers.