Composite Insulating Layers for Strain Control in SOI Transistors
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Solution Overview
Problem
Current semiconductor-on-insulator (SOI) architectures face challenges in optimizing carrier mobility within transistor channel regions, particularly due to variations in stress levels across n-channel and p-channel transistors, which affect drain current and transconductance.
Innovation Solution
A composite insulating layer with different strains is formed, where a tensile layer is used over the field isolation region and a compressive layer is incorporated within an opening in the tensile layer, serving as an etch stop layer to adjust the etching area and reduce process variation while maintaining strain consistency in the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dual stressor layer is used before forming the PMD layer, then carrier mobility in n-channel and p-channel transistors is improved, but the etch-stop layer area extends into the active region which causes process variation and affects drain current
Solution Approach 1:
The etch-stop layer is segmented into two distinct parts: a first etch-stop layer formed over the n-channel transistor structures and a second etch-stop layer formed over the p-channel transistor structures. This segmentation allows each etch-stop layer to be independently controlled and optimized for its respective transistor type, preventing the area extension problem while maintaining the stress benefits for carrier mobility enhancement.
Solution Approach 2:
Different etch-stop layers are applied to different regions of the substrate based on the local transistor type. The first etch-stop layer is specifically positioned over n-channel structures while the second etch-stop layer is positioned over p-channel structures, allowing localized optimization of stress characteristics and etch-stop functionality without affecting adjacent regions.
2Manufacturing precision
If the etch-stop layer area is reduced to improve manufacturing precision, then process variation is reduced, but the stress effect on carrier mobility is diminished
Solution Approach 1:
By dividing the etch-stop layer into separate first and second etch-stop layers for n-channel and p-channel structures respectively, each layer can be precisely controlled in area to stop exactly at the intended boundary without extending into the active region, while still providing sufficient stress coverage to enhance carrier mobility in the respective transistor types.
Solution Approach 2:
The solution changes the parameters of the etch-stop layer configuration by using multiple distinct layers with different areas and positions rather than a single uniform layer. This allows optimization of both the area control parameter (to prevent active region extension) and the stress parameter (to maintain carrier mobility enhancement) simultaneously.
Data Source
AI summary
An electronic device can include a field isolation region and a first insulating layer having a first strain and having a portion, which from a top view, lies entirely within the field isolation region. The electronic device can also include a second insulating layer having a second strain different from the first strain and including an opening. From a top view, the portion of the first insulating layer can lie within the opening in the second insulating layer. In one embodiment, the field isolation region can include a dummy structure and the portion of the first insulating layer can overlie the dummy structure. A process of forming the electronic device can include forming an island portion of an insulating layer wherein from a top view, the island portion lies entirely within the field isolation region.