Composite Interconnect Layout Using Lithography-Free Selective Deposition
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Solution Overview
Problem
The manufacturing and integration of semiconductor devices are increasingly complex, leading to inefficiencies and increased costs due to the need for numerous and complicated manufacturing operations.
Innovation Solution
A semiconductor device structure with a composite interconnect structure is developed, featuring lower and upper semiconductor structures made of different materials, separated by oxide portions and covered by a dielectric layer, allowing selective deposition of upper structures without costly lithographic steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional lithographic steps are used for depositing upper semiconductor structures, then manufacturing precision can be maintained, but manufacturing complexity and costs increase
Solution Approach 1:
The patent extracts and removes the lithographic step from the manufacturing process. By using selective area deposition directly on the lower semiconductor structure, the complex lithography process (which includes photoresist coating, patterning, and etching) is eliminated entirely, while still achieving precise material placement in the desired locations.
Solution Approach 2:
The lower semiconductor structure serves as its own deposition template. The selective area deposition process uses the inherent geometry and material properties of the lower structure to guide where upper semiconductor materials will deposit, eliminating the need for external lithographic patterning while maintaining manufacturing precision.
2Manufacturing precision
If traditional lithographic steps are used for depositing upper semiconductor structures, then pattern accuracy can be achieved, but processing time increases
Solution Approach 1:
The patent extracts and removes the lithographic step from the manufacturing process. By using selective area deposition directly on the lower semiconductor structure, the complex lithography process (which includes photoresist coating, patterning, and etching) is eliminated entirely, while still achieving precise material placement in the desired locations.
Solution Approach 2:
The patent skips the entire lithography sequence by implementing selective area deposition that directly places materials in their final positions based on the lower semiconductor structure's geometry, dramatically reducing the number of process steps and overall manufacturing time.
3Adaptability or versatility
If multiple separate manufacturing operations are used for integration, then device functionality can be achieved, but manufacturing costs increase
Solution Approach 1:
The patent merges multiple separate manufacturing operations into a single selective area deposition process. Instead of performing lithography, etching, and deposition as separate steps, the invention combines these functions into one operation that directly deposits upper semiconductor materials in their final positions, reducing manufacturing complexity and cost while maintaining full device functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs and processing time by eliminating the need for lithographic steps, while maintaining structural integrity and functionality.
Implementation Method 1
a first oxide portion disposed over the semiconductor substrate and extending along the second sidewall of the first lower semiconductor structure
Implementation Method 2
The materials of the upper semiconductor structure and the lower semiconductor structure are selected such that the upper semiconductor structure can be selectively deposited on the exposed surfaces of the lower semiconductor structure
Data Source
AI summary
A semiconductor device structure includes a first lower semiconductor structure disposed over a semiconductor substrate. The first lower semiconductor structure has a first sidewall and a second sidewall opposite to the first sidewall. The semiconductor device structure also includes a first upper semiconductor structure covering a top surface and the first sidewall of the first lower semiconductor structure. The first lower semiconductor structure and the first upper semiconductor structure include different materials. The semiconductor device structure further includes a first oxide portion disposed over the semiconductor substrate and extending along the second sidewall of the first lower semiconductor structure. The first oxide portion has an L-shape.