Composite Middle Interconnectors for Stress-Resilient Chip Packaging
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Solution Overview
Problem
The scaling down of semiconductor devices poses challenges in achieving improved quality, yield, performance, and reliability due to issues such as destructive stress forces during fabrication and operation.
Innovation Solution
The design incorporates middle and bottom interconnectors with varying densities and cavities, which neutralize potential destructive stress forces by redistributing strains and improving mechanical integrity, allowing for more flexible design rules and enhanced semiconductor device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are scaled down to improve computing ability, then device density and integration are improved, but destructive stress forces and reliability issues increase
Solution Approach 1:
The patent applies local quality by varying the density of middle interconnectors in different regions. Specifically, the density of middle interconnectors is adjusted based on the local requirements of different dies - higher density regions for dies requiring more interconnections and lower density regions where fewer interconnections are needed. This localized optimization reduces overall stress forces while maintaining necessary connectivity, thereby improving reliability without sacrificing computing ability.
Solution Approach 2:
The patent implements parameter changes by modifying the density parameter of middle interconnectors. The density is changed from uniform to variable, with different density values assigned to different topographical regions aligned with different dies. This parameter variation allows the structure to accommodate stress forces better, reducing destructive effects during scaling down while maintaining the required interconnection functionality for high computing ability.
2Ease of manufacture
If uniform density interconnectors are used, then manufacturing simplicity is maintained, but design flexibility and stress distribution are limited
Solution Approach 1:
The patent transitions from uniform to non-uniform interconnector density distribution. Different regions of the package structure have different interconnector densities tailored to their specific functional requirements. This local differentiation enhances design flexibility, allowing optimization for stress distribution, thermal management, and electrical connectivity in different areas, while still maintaining manufacturability through systematic fabrication processes.
3Quantity of substance
If interconnector density is increased to improve connectivity, then interconnection capability is improved, but stress forces and manufacturing complexity increase
Solution Approach 1:
The patent applies local quality by implementing spatially varying interconnector density. High-density interconnector regions are placed only where high interconnection capability is required by specific dies, while low-density regions are used where fewer connections are needed. This localized approach achieves the necessary quantity of interconnections for improved connectivity while avoiding the manufacturing complexity and stress forces that would result from uniformly high density throughout the entire package structure.
Data Source
AI summary
The present application discloses a semiconductor device. The semiconductor device includes a package structure including a first side and a second side opposite to the first side; an interposer structure positioned over the first side of the package structure; a first die positioned over the interposer structure; a second die positioned over the interposer structure; and a plurality of middle interconnectors positioned between the first side of the package structure and the first die and between the first side of the package structure and the second die. The plurality of middle interconnectors respectively includes a middle exterior layer positioned between the first side of the package structure and the interposer structure, a middle interior layer enclosed by the middle exterior layer, and a cavity enclosed by the interposer structure, the package structure, and the middle interior layer.