Composite Interface Circuit for Multi-Voltage UART
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Solution Overview
Problem
Existing universal asynchronous receiver/transmitter circuits fail to enable efficient data communications among multiple microprocessor-containing devices with different operating voltages and do not support high baud rates for full duplex universal asynchronous data communication interfaces.
Innovation Solution
A composite interface circuit is designed with bidirectional single-conductor buses and switching circuits, including transistors and pull-up resistors, to facilitate data communications between full duplex universal asynchronous data communication interfaces with different voltages, by increasing the rate of rise of parasitic capacitance, allowing for faster cycling and higher baud rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If existing universal asynchronous receiver/transmitter circuits are used, then data communications can be established, but efficient data communications among multiple devices with different operating voltages cannot be achieved
Solution Approach 1:
The patent introduces a voltage level translator as an intermediary component between devices operating at different voltages. This translator converts voltage levels from one domain to another, enabling seamless communication between 5V and 3.3V devices without direct connection, thus resolving the voltage compatibility issue while maintaining communication efficiency.
Solution Approach 2:
The patent modifies the electrical parameters (voltage levels) of the communication signals to accommodate different operating voltage domains. By dynamically adjusting voltage thresholds and signal levels, the system achieves compatibility across multiple voltage domains while preserving high-speed data transmission capabilities.
2Speed
If existing universal asynchronous receiver/transmitter circuits are used, then basic data communication is possible, but high baud rates for full duplex communication are not supported
Solution Approach 1:
The patent implements dynamic voltage threshold detection and adaptive sampling timing that adjusts to the actual signal characteristics. This dynamic adaptation allows the receiver to reliably detect signals at high baud rates by continuously optimizing its detection parameters, thereby maintaining communication stability even at elevated speeds.
Solution Approach 2:
The patent incorporates feedback mechanisms that monitor signal quality and adjust communication parameters in real-time. This feedback loop enables the system to maintain reliable communication at high baud rates by automatically correcting for signal degradation, noise, and timing variations that occur at higher speeds.
3Reliability
If voltage dividers are used to reduce voltage, then breakdown voltage of transistors is avoided, but communication speed is reduced
Solution Approach 1:
The patent segments the voltage reduction function into multiple stages using a cascaded voltage divider network. This segmentation allows each stage to operate within safe voltage ranges while collectively achieving the required voltage reduction, thereby minimizing the impact on signal rise time and communication speed compared to a single-stage divider.
Data Source
AI summary
Composite interface circuit including bidirectional single-conductor bus, first switching circuit, and second switching circuit. Bidirectional single-conductor bus is coupled by first pull-up resistor (R1) with first direct current (“DC”) input current source having first voltage (V1). First switching circuit includes first transistor (T1) being coupled with first pull-up resistor (R1) and with bidirectional single-conductor bus. Second switching circuit includes second transistor (T2) being coupled by second pull-up resistor (R2) with second DC input current source having second voltage (V2). Second switching circuit further includes voltage divider coupling second transistor (T2) with bidirectional single-conductor bus. First and second switching circuits are respectfully configured for being coupled with first transmitter conductor (Tx1) and first receiver conductor (Rx1) of full duplex universal asynchronous data communication interface.