Composite Interposer Packaging for Shorter Signal Paths and Heat Dissipation
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Solution Overview
Problem
Multi-chip module packages with large interposers suffer from degradation in computing speed due to long signal transmission paths and heat accumulation, and their large size makes them difficult to integrate into high-performance computing systems.
Innovation Solution
A composite chip package structure is developed, featuring a composite interposer with an in-interposer semiconductor chip, a dielectric matrix, and redistribution structures on both sides, along with a ceramic-based composite packaging substrate that enhances heat dissipation and reduces package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional multi-chip module packages with large interposers are used, then computing capabilities can be provided, but signal transmission paths become long causing degradation in computing speed
Solution Approach 1:
The patent transitions from planar signal transmission to three-dimensional vertical transmission by stacking semiconductor dies and interposers in multiple layers. Through-silicon vias (TSVs) enable signals to travel vertically through the stack rather than laterally across large distances, dramatically reducing transmission path length and improving computing speed.
Solution Approach 2:
The patent implements a nested structure where semiconductor dies are mounted on interposers, which are then stacked with additional dies and interposers forming a multi-layer tower. This nested arrangement allows compact integration of multiple computing components while maintaining short signal paths through vertical interconnections.
2Reliability
If traditional multi-chip module packages with large interposers are used, then computing capabilities can be provided, but heat accumulation occurs degrading semiconductor die performance
Solution Approach 1:
The patent extracts heat from the semiconductor die by introducing dedicated heat dissipation structures, including heat sinks attached to the interposer base and thermal vias that conduct heat away from active regions. This separation of heat generation and heat dissipation pathways prevents thermal accumulation and maintains semiconductor performance.
Solution Approach 2:
The patent employs composite interposer structures combining materials with different thermal properties - such as diamond-like carbon coatings for thermal conduction, ceramic layers for heat distribution, and metal heat sinks for heat dissipation. This multi-material approach optimizes both thermal management and electrical performance.
3Adaptability or versatility
If traditional multi-chip module packages with large interposers are used, then computing capabilities can be provided, but the large package size makes integration into high-performance computing systems difficult
Solution Approach 1:
The patent converts the package architecture from a large two-dimensional layout to a compact three-dimensional vertical stack. By arranging computing components in multiple layers stacked vertically, the system achieves high computing capability in a small footprint, dramatically improving integratability into high-performance computing systems with limited space.
Solution Approach 2:
The patent merges multiple functional components - semiconductor dies, interposers, heat dissipation structures, and interconnection layers - into a single integrated three-dimensional package. This consolidation eliminates the need for separate mounting of individual components, reducing overall system size and improving adaptability.
Data Source
AI summary
A chip package structure includes: a composite interposer including at least one in-interposer semiconductor chip including a respective semiconductor circuitry therein, a dielectric matrix laterally surrounding the at least one in-interposer semiconductor chip, a die-side redistribution structure located on a first side of the dielectric matrix, and a substrate-side redistribution structure located on a second side of the dielectric matrix; and at least one semiconductor die attached to the die-side redistribution structure through a respective array of solder material portions.