Composite Isolation Structure for Dense Gate-All-Around Fin Layouts
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Solution Overview
Problem
Existing isolation structures in semiconductor integrated circuits are inadequate in isolating active region segments, leading to increased complexity and potential electrical shorting, which hampers the scaling down process and device performance.
Innovation Solution
The implementation of continuous poly on diffusion edge (CPODE) structures, which are formed between device boundaries to minimize separation distance without compromising performance, using a method that involves patterning sacrificial layers and replacing them with composite isolation structures to create gate-all-around transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing isolation structures are used to divide active regions, then device isolation is achieved, but device density is reduced due to increased separation distance
Solution Approach 1:
The isolation structure transitions from a traditional planar configuration to a multi-dimensional structure that extends vertically into the trench. The dielectric material fills the trench depth, creating isolation in the vertical dimension while minimizing horizontal separation distance, thereby maintaining device density while achieving effective isolation.
Solution Approach 2:
The isolation structure is nested within the trench formed between adjacent active regions. The dielectric material is contained within the trench boundaries, allowing the isolation function to be integrated into the existing device layout without requiring additional lateral space, thus preserving device density while providing effective isolation.
2Productivity
If separation distance between devices is reduced to increase density, then device density improves, but electrical shorting and current leakage increase
Solution Approach 1:
By extending the isolation structure vertically into the trench, the patent creates an additional dimension of electrical isolation. This vertical isolation barrier effectively blocks current leakage paths even when horizontal separation distances are minimized, allowing high device density without compromising electrical isolation.
Solution Approach 2:
The dielectric material acts as an intermediary barrier between adjacent active regions. It is positioned within the trench to provide electrical isolation, mediating the interaction between neighboring devices and preventing direct electrical contact that would cause shorting or leakage, thus enabling reduced separation distances.
3Ease of manufacture
If conventional isolation structures are used, then manufacturing process is simpler, but device performance deteriorates due to current leakage
Solution Approach 1:
The isolation structure is segmented into multiple components: the trench formation step, the dielectric material deposition, and the planarization layer. This segmentation allows each function to be optimized independently - the trench provides structural definition, the dielectric provides electrical isolation, and the planarization provides surface preparation for subsequent processing, thereby improving device performance while maintaining manufacturing feasibility.
Solution Approach 2:
The trench isolation structure serves multiple functions simultaneously: it provides mechanical separation between devices, creates a containment volume for the dielectric isolation material, and establishes a planar reference surface for subsequent processing layers. This multi-functionality achieves improved device performance without proportionally increasing manufacturing complexity.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a first device, a second device, and a composite isolation structure. The first device includes a first fin structure and a first gate structure. The first fin structure is disposed over the semiconductor substrate and includes a first channel region. The first gate structure wraps around the first channel region. The second device includes a second fin structure and a second gate structure. The second fin structure is disposed over the semiconductor substrate and includes a second channel region. The second gate structure wraps around the second channel region. The composite isolation structure is disposed between the first and second devices and includes first and second dielectric layers. The second dielectric layer is sandwiched between the semiconductor substrate and the first dielectric layer. A topmost surface of the second dielectric layer is lower than a bottom surface of the first channel region.