Composite Landing Pad for Semiconductor Interconnect Alignment
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Solution Overview
Problem
The complexity of manufacturing semiconductor devices leads to misalignment issues in interconnect structures, which affects the performance and yield rate of these devices.
Innovation Solution
A semiconductor device design featuring a composite landing pad formed by an inner and outer silicide portion, surrounded by a barrier layer, which increases the landing area for upper metal plugs, reducing contact resistance and misalignment issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If manufacturing operations are increased for integration of various semiconductor devices, then device functionality and integration are improved, but misalignment in interconnect structures occurs
Solution Approach 1:
The patent applies preliminary action by forming a composite landing pad structure before upper metal plug deposition. The landing pad includes a lower metal plug, barrier layer, and silicide portions that are pre-configured to provide alignment tolerance. This preliminary structure compensates for potential misalignment during subsequent manufacturing steps, allowing increased device integration without sacrificing alignment precision.
Solution Approach 2:
The patent employs composite materials by creating a multi-material landing pad structure consisting of different metal layers, barrier materials, and silicide portions. This composite structure provides both electrical connectivity and mechanical alignment tolerance, resolving the contradiction between increased functionality and maintained alignment precision through material diversity and structural complexity.
2Ease of manufacture
If conventional single-layer landing pad is used, then manufacturing process is simple, but contact resistance is high and misalignment issues occur
Solution Approach 1:
The patent applies segmentation by dividing the landing pad into multiple functional segments: a lower metal plug for electrical connection, a barrier layer for diffusion prevention, and silicide portions for reduced contact resistance. This segmented structure improves reliability by addressing multiple functional requirements simultaneously while maintaining a manageable manufacturing process through systematic layer-by-layer formation.
Solution Approach 2:
The patent transitions from a conventional single-layer landing pad to a multi-dimensional composite structure with vertical layering and horizontal extent. The silicide portions extend laterally beyond the lower metal plug, creating a stepped configuration that provides both electrical connectivity and alignment tolerance in multiple spatial dimensions, thereby reducing contact resistance without significantly complicating the manufacturing process.
Data Source
AI summary
The present disclosure relates to method for preparing a semiconductor device with a composite landing pad. The method includes forming a first dielectric layer over a semiconductor substrate. The semiconductor device also includes forming a lower metal plug and a barrier layer in the first dielectric layer. The lower metal plug is surrounded by the barrier layer. The semiconductor device further includes forming an inner silicide portion over the lower metal plug, and an outer silicide portion over the barrier layer. A topmost surface of the outer silicide portion is higher than a topmost surface of the inner silicide portion.