Composite Logic Gate Circuit With Fewer Transistors and Lower Power
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Solution Overview
Problem
Current integrated circuit designs face challenges due to the limitations of traditional Boolean logic, particularly in terms of power consumption and area, as they require more transistors and consume more power compared to Reed-Muller logic-based designs, which are not widely adopted due to the lack of suitable low-power cell libraries.
Innovation Solution
A composite logic gate circuit design that includes a simple logic gate circuit and PMOS and NMOS transistors, where the logic gate circuit can be configured as an AND or OR gate, and an inverter circuit, implemented using pass transistor logic to reduce the number of transistors and power consumption, such as in the AND-XOR or OR-XOR gate circuits, by borrowing inverter circuits from existing designs and adding minimal additional transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional Boolean logic gate circuits (AND, OR, NOT) are used to implement digital circuits, then the circuits can be implemented with well-established design methodologies, but the circuits require more transistors and consume more power compared to Reed-Muller logic
Solution Approach 1:
The patent changes the logical parameter from traditional Boolean logic to Reed-Muller logic (AND-XOR or OR-XOR operations), which fundamentally alters how logic functions are implemented. This parameter change enables reduced transistor count and lower power consumption while maintaining design feasibility through the provided transistor-level circuit structures
2Use of energy by stationary object
If Reed-Muller logic (AND-XOR, OR-XOR) is used to reduce power consumption and area, then the transistor count and power consumption are reduced, but suitable low-power cell libraries are lacking
Solution Approach 1:
The patent segments the Reed-Muller logic implementation into basic transistor-level building blocks (AND gate with inverter, OR gate with inverter, and XOR functionality using PMOS and NMOS transistors). This segmentation creates modular, reusable circuit units that can be assembled into complete logic functions, effectively creating a cell library from first principles
Solution Approach 2:
The patent creates standardized copied structures for Reed-Muller logic gates by defining specific transistor configurations that can be replicated. The inverter circuits and logic gate structures are designed as reusable templates that can be copied and combined to implement various logic functions, establishing a manufacturable cell library
3Adaptability or versatility
If AND-XOR gate circuits are implemented by cascading AND gate with XOR gate, then the logic function is achieved, but the area and power consumption are large
Solution Approach 1:
The patent merges the AND gate and XOR gate functionalities into a single integrated transistor-level circuit structure. By combining these functions at the transistor level rather than cascading separate gate circuits, the design achieves the AND-XOR logic function with reduced area and lower power consumption while maintaining full logic functionality
4Reliability
If more transistors are used in traditional Boolean logic circuits, then the circuits can be implemented with standard logic gates, but the area and power consumption increase
Solution Approach 1:
The patent changes the fundamental parameter of logic operation from Boolean to Reed-Muller, which allows the same logical functionality to be achieved with fewer transistors. The transistor-level design optimizes the circuit to use minimal transistor count while maintaining reliable logic operations, directly reducing circuit area
Data Source
AI summary
The present disclosure relates to a composite logic gate circuit, including: a simple logic gate circuit including a first logic gate circuit and an inverter circuit, a first PMOS transistor, and a first NMOS transistor. The first logic gate circuit is configured to receive a first input signal and a second input signal, and to output a first output signal. The inverter circuit includes a second PMOS transistor and a second NMOS transistor. A source of the second PMOS transistor is coupled to a power input terminal, a drain is coupled to a drain of the second NMOS transistor, and a gate is configured to receive the first output signal. A source of the second NMOS transistor is coupled to a ground terminal, and a gate is configured to receive the first output signal. A source of the first PMOS transistor is coupled to the drain of the second PMOS transistor, a drain is coupled to a drain of the first NMOS transistor, and a gate is configured to receive a third input signal. A source of the first NMOS transistor is configured to receive the first output signal, and a gate is configured to receive the third input signal. The simple logic gate circuit is an AND or OR gate circuit, and the first logic gate circuit is a NAND or NOR gate circuit.