Composite Metal Gate Electrodes for CMOS Transistors
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Solution Overview
Problem
Conventional MOS transistor manufacturing methods face challenges in forming gate electrodes with different metals for n-MOS and p-MOS transistors, leading to variations in threshold voltages and potential operational deterioration due to voids in the metal layers.
Innovation Solution
A method involving the formation of a gate insulating layer, a dummy gate electrode, and electrically insulating spacers, followed by deposition and selective etching of metal layers to create composite metal gate electrodes, ensuring no voids and allowing for the use of different metals for n-MOS and p-MOS transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different metals are used for n-MOS and p-MOS gate electrodes to achieve different threshold voltages, then device performance is improved, but manufacturing complexity increases due to the need for selective metal deposition and etching processes
Solution Approach 1:
The gate electrode formation process is segmented into distinct stages: dummy gate formation, spacer formation, selective dummy gate removal, and metal layer deposition. This segmentation allows different metal layers to be deposited selectively for n-MOS and p-MOS transistors without requiring complex simultaneous deposition processes, thereby managing manufacturing complexity while achieving different threshold voltages
Solution Approach 2:
Dummy gate electrodes are formed in advance before metal gate formation. These dummy gates serve as placeholders that define the gate region and enable subsequent selective removal processes. This preliminary action simplifies the overall manufacturing process by establishing the gate structure framework before introducing the complex different-metal requirement
2Reliability
If metal layers are deposited to form gate electrodes, then electrical conductivity is improved, but voids may form in the metal layers leading to operational deterioration
Solution Approach 1:
A filler layer is introduced as an intermediary between the metal layers and the dummy gate structure. This filler layer serves multiple functions: it provides a stable base for metal deposition, prevents void formation during subsequent etching processes, and ensures complete metal layer coverage. The intermediary filler layer acts as a buffer that eliminates the harmful voids while preserving the high conductivity benefit of metal gates
Solution Approach 2:
The filler layer is deposited beforehand to cushion and prevent the formation of voids in the metal layers. By providing this protective layer in advance, the process ensures that subsequent metal deposition and etching steps will not create voids that would compromise electrical conductivity, thus preventing operational deterioration before it can occur
3Adaptability or versatility
If dummy gate electrodes are removed selectively to form metal gates, then different metal compositions can be achieved for n-MOS and p-MOS, but process time increases due to multiple deposition and etching steps
Solution Approach 1:
Multiple operations are merged into unified process steps: the filler layer deposition is combined with the first metal layer deposition, and the selective dummy gate removal is combined with the formation of the second metal layer. This merging reduces the total number of separate process steps, thereby decreasing manufacturing cycle time while still enabling different metal compositions for n-MOS and p-MOS transistors
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents operational characteristic deterioration of p-MOS transistors by eliminating voids in the gate electrodes and allows for the use of different metals, enhancing the manufacturing process productivity and consistency.
Implementation Method 1
A first metal layer is deposited onto an upper surface of the mold layer and onto inner sidewalls of the spacers
Implementation Method 2
The dummy gate electrode is then removed from between the spacers by selectively etching back the dummy gate electrode using the mold layer and the spacers as an etching mask
Data Source
AI summary
Provided is a method for manufacturing a MOS transistor. The method comprises providing a substrate having a first active region and a second active region; forming a dummy gate stack on the first active region and the second active region, the dummy gate stack comprising a gate dielectric layer and a dummy gate electrode; forming source/drain regions in the first active region and the second active region disposed at both sides of the dummy gate stack; forming a mold insulating layer on the source/drain region; removing the dummy gate electrode on the first active region to form a first trench on the mold insulating layer; forming a first metal pattern to form a second trench at a lower portion of the first trench, and removing the dummy gate electrode on the second active region to from a third trench on the mold insulating layer; and forming a second metal layer in the second trench and the third trench to form a first gate electrode on the first active region and a second gate electrode on the second active region.