Composite Molding Compound for Semiconductor Package Planarization
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Solution Overview
Problem
Current three-dimensional integration technologies for wafer-level packaging face challenges in achieving high-density integration and reliable interconnects, particularly in ensuring proper encapsulation and planarization of semiconductor packages to enhance yield and reduce costs.
Innovation Solution
A manufacturing method involving a carrier with a buffer layer, through interlayer vias, and a composite molding compound structure, where a polymeric molding compound is used to encapsulate and planarize the semiconductor chips and vias, allowing for better surface flatness and structural integrity, and enabling efficient debonding and dicing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional molding compound structures are used, then manufacturing process is simpler, but surface flatness and encapsulation quality deteriorate
Solution Approach 1:
The molding compound structure is divided into multiple distinct layers: a first molding compound layer and a second molding compound layer with different material compositions. This segmentation allows each layer to perform specific functions - the first layer provides structural support while the second layer achieves superior surface flatness, thereby resolving the contradiction between manufacturing precision and structural complexity.
Solution Approach 2:
The patent employs composite materials by combining different molding compound formulations in separate layers. The first molding compound and second molding compound have distinct material properties that complement each other, enabling the structure to achieve both structural integrity and high surface flatness simultaneously.
2Productivity
If high-density integration is pursued, then performance improves, but packaging complexity and cost increase
Solution Approach 1:
The patent transitions from planar packaging to three-dimensional vertical stacking architecture. Multiple semiconductor chips are stacked in the vertical dimension and interconnected through through-silicon vias (TSVs), enabling high-density integration without increasing lateral packaging complexity. This dimensional change allows high productivity while maintaining manageable packaging structure.
Solution Approach 2:
The packaging structure employs nested arrangements where semiconductor chips, TSVs, and molding compound layers are organized in concentric and hierarchical patterns. The TSVs are embedded within chips, which are stacked within the molding compound structure, creating a compact nested configuration that achieves high integration density with controlled complexity.
3Reliability
If encapsulation quality is improved, then reliability increases, but manufacturing process complexity increases
Solution Approach 1:
The patent performs preliminary encapsulation actions by forming the first molding compound layer to provide initial structural support and protection before adding the second molding compound layer. This staged approach ensures proper encapsulation quality is established early in the process, with subsequent layers building upon this foundation rather than requiring complete re-encapsulation.
Data Source
AI summary
A manufacturing method for semiconductor packages is provided. Chips are provided on a carrier. Through interlayer vias are formed over the carrier to surround the chips. A molding compound is formed over the carrier to partially and laterally encapsulate the chip and the through interlayer vias. The molding compound comprises pits on a top surface thereof. A polymeric molding compound is formed on the molding compound to fill the pits of the molding compound.