Composite MTJ Spacer Structure for Sub-40 Nm Alignment Control

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Solution Overview

Problem

Advanced semiconductor manufacturing techniques face misalignment and overlay problems when feature sizes reach below 40 nm, degrading device performance and reducing yield in storage devices like MRAM, RRAM, and CBRAM.

Innovation Solution

A method involving the formation of a semiconductor storage device with a composite spacer, comprising a spacer film and a barrier layer, where the spacer film is conformally deposited over a stacked feature and the barrier layer is etched to create a specific shape with a notch and a standing portion, addressing misalignment issues by forming a spacer with a unique geometry that enhances etching resistance and control.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional spacer structures are used in advanced semiconductor manufacturing, then manufacturing process simplicity is maintained, but misalignment and overlay problems occur when feature sizes reach below 40 nm

Engineering Contradiction:
Improvealignment precisionVSAvoidspacer structure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The spacer structure is segmented into multiple functional layers: a first spacer layer conformally deposited on the mandrel, and a second spacer layer deposited thereon. This segmentation allows each layer to serve specific functions - the first layer provides baseline spacing while the second layer enables precise alignment control through selective etching, thereby resolving the misalignment issues in sub-40nm manufacturing without requiring complete structural redesign

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first spacer layer acts as an intermediary between the mandrel and the second spacer layer. It provides a foundation that controls the thickness and positioning of the second spacer layer, enabling precise alignment while simplifying the overall manufacturing process. The intermediary structure allows incremental control of alignment precision without requiring complete complexity overhaul

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If feature sizes are reduced below 40 nm to increase device density, then productivity is improved, but misalignment problems degrade device performance and reduce yield

Engineering Contradiction:
Improvedevice densityVSAvoiddevice performance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The method performs preliminary alignment preparation by conformally depositing the first spacer layer on the mandrel before forming the second spacer layer. This preliminary action establishes a controlled foundation that pre-compensates for potential misalignment issues, allowing subsequent processing steps to maintain high precision even as feature sizes are reduced to increase device density

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention changes the physical and chemical parameters of the spacer structure by using different materials for the first and second spacer layers with distinct etch selectivities. This parameter change enables differential etching processes that precisely control the final spacer geometry, maintaining reliability in sub-40nm devices while allowing higher density packaging

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces misalignment and improves manufacturing yield by forming a semiconductor storage device with a composite spacer that maintains device performance even in the presence of misalignment, ensuring reliable operation and increased precision in smaller feature sizes.

Implementation Method 1

the spacer film is conformally deposited over a stacked feature

Methodology Applied
Scientific EffectConformal deposition: Physical Vapour Deposition

Implementation Method 2

the barrier layer is etched to create a specific shape with a notch and a standing portion

Methodology Applied
Scientific EffectEtching:

Data Source

PatentUS11800822B2Memory device with composite spacer
Publication Date: 2023.10.24 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11800822B2 patent drawing
  • US11800822B2 patent drawing
  • US11800822B2 patent drawing

AI summary

A memory device includes a bottom electrode, a magnetic tunnel junction (MTJ) structure, an inner spacer, and an outer spacer. The MTJ structure is over the bottom electrode. The bottom electrode has a top surface extending past opposite sidewalls of the MTJ structure. The inner spacer contacts the top surface of the bottom electrode and one of the opposite sidewalls of the MTJ structure. The outer spacer contacts an outer sidewall of the inner spacer. The outer spacer protrudes from a top surface of the inner spacer by a step height.