Sequenced Composite NMOS Switching for Faster High-Side Turn-On
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Solution Overview
Problem
Existing semiconductor switch control methods, particularly for output stages, face challenges in quickly turning on high-side NMOS switches due to limited charge transfer capability of voltage generation circuitry, leading to high resistance during turn-on transitions, which results in power losses and efficiency reduction.
Innovation Solution
A composite semiconductor switch formed from multiple NMOS switch elements, where the gate electrodes are driven in a temporally sequenced manner to minimize average switch resistance during transitions, allowing for efficient use of limited charge transfer capability and faster turn-on times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a single NMOS switch is used for high-side switching, then the circuit area is minimized, but the turn-on time increases and average resistance increases due to limited charge transfer capability
Solution Approach 1:
The single NMOS switch is segmented into multiple parallel NMOS switches (first NMOS switch and second NMOS switch). Each switch has its own gate electrode that can be independently controlled. This segmentation allows the charge pump to charge multiple smaller gate capacitances in parallel rather than one large capacitance, enabling faster turn-on while keeping the total on-resistance low through the parallel configuration.
2Device complexity
If a single NMOS switch is used for high-side switching, then the device complexity is minimized, but the average switch resistance during transition increases leading to power losses
Solution Approach 1:
The switch is divided into multiple parallel NMOS switches with independent gate control. This allows selective activation of switches based on charge availability, optimizing the transition process to minimize resistance and power loss without requiring complex overall device architecture.
Solution Approach 2:
The controller enables the first NMOS switch before the second NMOS switch during the turn-on transition. This preliminary action allows the charge pump to initially charge the gate of the first switch, establishing a conductive path before engaging the second switch, thereby minimizing the average resistance and power loss during the transition process.
3Speed
If gate electrodes are driven simultaneously, then the switching speed is maximized, but the charge transfer capability of the voltage generation circuitry is insufficient leading to high average resistance
Solution Approach 1:
The gate driving is segmented into sequential phases rather than simultaneous driving. The controller first enables the first NMOS switch and charges its gate, then subsequently enables the second NMOS switch. This segmentation matches the charge transfer capability of the voltage generation circuitry, allowing reliable charging of each gate without requiring excessive simultaneous charge transfer.
Solution Approach 2:
The first NMOS switch is enabled and its gate is charged in advance before the second NMOS switch is enabled. This preliminary action ensures that the charge pump has sufficient time to charge the first gate capacitance before needing to charge the second, making effective use of the limited charge transfer capability while still achieving fast overall switching.
4Quantity of substance
If the high-side switch turns on slowly, then the charge transfer capability requirements are reduced, but the average resistance increases causing efficiency reduction
Solution Approach 1:
The switch is segmented into multiple parallel NMOS switches. Even though the charge transfer capability is limited, the segmentation allows the available charge to be distributed to multiple smaller gate capacitances, enabling faster turn-on of each individual switch and reducing the average resistance during transition, thereby improving overall switching efficiency.
Solution Approach 2:
The controller implements preliminary enabling of the first NMOS switch before the second NMOS switch. This allows the charge pump to efficiently charge the first gate capacitance first, establishing a low-resistance path early in the transition, which improves switching efficiency without requiring high charge transfer capability from the voltage generation circuitry.
Data Source
AI summary
This application relates to methods and apparatus for switching control of semiconductor switches. In a switching circuit, a semiconductor switch is implemented as a composite switch having a plurality of switch elements, each having a respective gate electrode. A switch driver is configured to drive the gate electrodes of the switch elements to a first gate voltage over a duration of a first switch transition and is configured to enable drive of at least some of the gate electrodes of the plurality of semiconductor switch elements at different times in a temporal sequence during the first switch transition. The temporal sequence is configured to provide an average resistance of the composite switch over the duration of the first switch transition which is closer to a final composite switch resistance, compared to driving the gate electrodes of the switch elements at the same time as one another.