Chip-Embedded Package Substrate With Composite Layer for Warpage Resistance

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Solution Overview

Problem

Conventional semiconductor packaging methods, such as coreless carrier-based techniques, face challenges with structural strength and warpage due to the lack of a hard core board, which affects the overall reliability and yield of the package structure.

Innovation Solution

A package structure and manufacturing method utilizing a composite layer of non-conductor inorganic and organic materials, including ceramic and polymer materials, to enhance structural strength, combined with a metal layer, sealant, chip with exposed electrode pads, circuit layer structure with conductive blind holes, and an insulating protective layer, which prevents warpage and improves reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If a coreless carrier is used to process chip embedded substrates, then the overall size is reduced and electrical functionality is improved, but structural strength is insufficient and warpage occurs easily

Engineering Contradiction:
Improveoverall sizeVSAvoidstructural strength
Core Design Contradiction:
Volume of moving objectVSStrength

Solution Approach 1:

The patent applies composite materials by creating a multi-layer structure consisting of a carrier substrate, a first reinforcing layer (e.g., ceramic or glass material), and a second reinforcing layer (e.g., metal or polymer material). This composite structure provides both the size reduction benefits of coreless carriers and the structural strength needed to prevent warpage, directly resolving the technical contradiction between miniaturization and structural integrity.

Inventive Principle:
Principle #40Composite materials

2Length of stationary object

If a coreless carrier is used to process chip embedded substrates, then structure thickness is reduced, but warpage occurs easily due to lack of hard core board support

Engineering Contradiction:
Improvestructure thicknessVSAvoidwarpage resistance
Core Design Contradiction:
Length of stationary objectVSStability of the object's composition

Solution Approach 1:

The patent employs composite materials with different mechanical properties in a layered configuration. The first reinforcing layer (ceramic/glass) provides dimensional stability and warpage resistance, while the second reinforcing layer (metal/polymer) adds structural support. This composite approach maintains reduced thickness while achieving the hard core board support effect needed to prevent warpage.

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The patent applies local quality by placing reinforcing layers at specific locations within the package structure where they are most needed for warpage prevention. The first reinforcing layer is positioned between the carrier substrate and the chip, while the second reinforcing layer is placed at the opposite side, providing localized structural support exactly where required to maintain stability without increasing overall thickness.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The composite layer provides increased hardness and structural strength, preventing warpage and enhancing both process yield and reliability of the package structure, while also facilitating effective heat dissipation through the metal layer.

Implementation Method 1

a composite layer of a non-conductor inorganic material and an organic material, including ceramic and polymer materials, to enhance structural strength

Methodology Applied
Scientific EffectComposite materials: Composite Materials

Implementation Method 2

facilitating effective heat dissipation through the metal layer

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS11895780B2Manufacturing method of package structure
Publication Date: 2024.02.06 UNIMICRON TECH CORP
  • US11895780B2 patent drawing
  • US11895780B2 patent drawing
  • US11895780B2 patent drawing

AI summary

A method of manufacturing package structures includes providing a carrier including a supporting layer, a metal layer, and a release layer between the supporting layer and the metal layer at first. Afterwards, a composite layer of a non-conductor inorganic material and an organic material is disposed on the metal layer. Then, a chip embedded substrate is bonded on the composite layer. Afterwards, an insulating protective layer having openings is formed on the circuit layer structure and exposes parts of the circuit layer structure in the openings. Afterwards, the supporting layer and the release layer are removed to form two package substrates. Then, each of the package substrates is cut.