Composite Redistribution Structure for Low-Loss Die Interconnects
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Solution Overview
Problem
Current high performance computing systems face challenges in achieving miniaturization, higher speed, and better electrical performance due to limitations in packaging and assembling techniques.
Innovation Solution
The development of a manufacturing method for a local interconnect component and a semiconductor package that includes the formation of conductive pillars, conductive connectors, and insulating layers, along with a redistribution structure, to facilitate efficient electrical connections and reduce transmission loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional packaging and assembling techniques are used, then manufacturing simplicity is maintained, but electrical performance deteriorates due to transmission loss and limited bandwidth
Solution Approach 1:
The patent segments the interconnect function into multiple components: conductive pillars within the substrate, conductive connectors on the surface, and redistribution structures. This segmentation allows each component to be optimized independently for electrical performance while managing complexity through modular design
Solution Approach 2:
The patent transitions from planar two-dimensional interconnections to three-dimensional vertical interconnections through conductive pillars extending through the substrate thickness. This dimensional change reduces transmission distance and improves electrical performance without increasing lateral footprint
2Area of moving object
If chip size is reduced for miniaturization, then device density is improved, but transmission loss increases due to smaller feature sizes and tighter spacing
Solution Approach 1:
The patent applies different material properties and structural characteristics to different regions: conductive pillars provide low-resistance vertical paths, while redistribution structures provide controlled impedance routing. This local optimization maintains signal integrity despite reduced overall chip dimensions
Solution Approach 2:
The patent employs composite interconnect structures combining multiple materials with complementary properties: conductive materials for low resistance, insulating materials for signal isolation, and potentially different metal layers for impedance matching. This composite approach reduces transmission loss in miniaturized structures
3Productivity
If higher speed communication is achieved through improved interconnects, then bandwidth is increased, but manufacturing precision requirements worsen due to tighter tolerances
Solution Approach 1:
The patent forms conductive pillars and insulating layers through the substrate before bonding operations. This preliminary structuring establishes precise interconnect geometries early in the manufacturing process, reducing the need for post-bonding alignment adjustments and relaxing final tolerance requirements
Solution Approach 2:
The patent introduces redistribution structures as intermediary elements between the conductive pillars and external connections. These intermediaries provide additional degrees of freedom for alignment compensation and signal routing, reducing the direct impact of manufacturing tolerances on final performance
Data Source
AI summary
A semiconductor structure includes a substrate component, an IC die component over the substrate component, and a composite redistribution structure interposed between and electrically coupled to the substrate and IC die components. The composite redistribution structure includes a local interconnect component between a first redistribution structure overlying the substrate component and a second redistribution structure underlying the IC die component, and an insulating encapsulation between the first and second redistribution structures and embedding the local interconnect component therein. The local interconnect component includes TSVs penetrating through a substrate and electrically coupled to first and second conductive connectors, the first conductive connectors between the first redistribution structure and a first side of the substrate, the second conductive connectors between the second redistribution structure and a second side of the substrate, and a first insulating layer between the first redistribution structure and the first side and laterally covering the first conductive connectors.