Semiconductor package including a redistribution structure
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Solution Overview
Problem
The rapid development of electronics demands more compact, multifunctional, and high-capacity semiconductor devices with increased connection terminals, necessitating a semiconductor package with reliable connections and efficient heat dissipation to reduce interference and thermal stress.
Innovation Solution
A semiconductor package design featuring a lower redistribution structure with a primary and secondary conductive structure, connection vias, and an upper encapsulant, along with conductive posts and a heat dissipation system, including first and second heat dissipation vias and a heat dissipation pad, to facilitate electrical connectivity and efficient heat dissipation while accommodating different thermal expansion coefficients.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If connection terminals are increased for high integration, then functionality and capacity are improved, but interference between terminals and thermal stress increase
Solution Approach 1:
The patent transitions from planar terminal arrangement to three-dimensional stacked configuration. Multiple connection terminals are arranged vertically across different layers (first connection terminals on first substrate, second connection terminals on second substrate), utilizing the vertical dimension to increase terminal count while maintaining horizontal spacing to reduce interference.
Solution Approach 2:
The connection terminal system is divided into multiple independent segments across different substrates and layers. Each substrate carries its own set of connection terminals, and conductive vias provide segmented electrical pathways between layers, allowing independent optimization of each segment to reduce overall interference.
2Quantity of substance
If more connection terminals are added to semiconductor chips, then device capacity increases, but thermal stress and reliability issues worsen
Solution Approach 1:
The patent distributes connection terminals across multiple vertical layers rather than concentrating them on a single plane. The first connection terminals are positioned on the first substrate, while second connection terminals are positioned on the second substrate at a different vertical level, enabling increased terminal quantity while dispersing thermal stress across three-dimensional space.
Solution Approach 2:
Conductive vias serve as intermediary elements that electrically connect the first connection terminals on the first substrate to the second connection terminals on the second substrate. These vias provide dedicated electrical pathways that separate signal transmission from thermal management functions, improving reliability by isolating electrical and thermal pathways.
3Area of stationary object
If connection terminals are spaced closer to increase density, then area efficiency improves, but interference between terminals increases
Solution Approach 1:
The patent resolves the area efficiency versus interference contradiction by moving the problem into the vertical dimension. Connection terminals that would be crowded on a single plane are instead distributed across multiple stacked substrates, allowing dense terminal placement within each layer while maintaining sufficient spacing between layers to prevent interference.
Solution Approach 2:
The terminal array is segmented into multiple independent groups on different substrates. Each substrate carries a subset of connection terminals with adequate spacing, and the overall system achieves high density through vertical stacking rather than horizontal compression, eliminating interference while maintaining area efficiency.
4Ease of manufacture
If thermal expansion coefficients of different materials are accommodated, then manufacturing flexibility improves, but structural complexity increases
Solution Approach 1:
The patent addresses thermal expansion differences by selecting materials for the first and second substrates with compatible thermal expansion coefficients. This parameter matching allows the multi-layer structure to expand and contract uniformly during manufacturing and operation, simplifying the manufacturing process despite the increased structural complexity of stacked substrates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design ensures reliable electrical connections and effective heat dissipation, reducing thermal stress and improving the reliability and performance of semiconductor packages by managing thermal expansion differences and enhancing heat dissipation capabilities.
Implementation Method 1
Conductive posts electrically connect the upper composite redistribution structure with the lower redistribution structure
Implementation Method 2
first heat dissipation vias passing through the primary conductive structure, and having one end contacting a top surface of the semiconductor device and the other end contacting the heat dissipation plate, second heat dissipation vias passing through the secondary conductive structure and having one end contacting the heat dissipation plate
Data Source
AI summary
A semiconductor package includes a lower redistribution structure. A semiconductor device is disposed on the lower redistribution structure. A lower encapsulant is disposed on the lower redistribution structure and surrounds a side surface of the semiconductor device. An upper composite redistribution structure is disposed on an upper portion of the semiconductor device and includes a primary conductive structure, a secondary conductive structure disposed on the primary conductive structure, connection vias disposed between the primary conductive structure and the secondary conductive structure, and an upper encapsulant disposed between the primary conductive structure and the secondary conductive structure and surrounding the connection vias.