Composite Semiconductor Channel for 3D Memory
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Solution Overview
Problem
In three-dimensional memory devices with horizontal source contact layers, controlling the diffusion of n-type dopants into vertical semiconductor channels is challenging due to the large grain size of polysilicon material and varying grain boundary orientations, leading to uneven dopant distribution and diffuse p-n junctions.
Innovation Solution
A composite semiconductor channel with different dopant concentrations and grain sizes is implemented, featuring a pedestal channel portion with high dopant concentration and a vertical channel with lower dopant concentration, along with a source contact layer to control n-type dopant diffusion, enhancing the abruptness of the junction and improving transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a horizontal source contact layer is used in three-dimensional memory devices, then the device structure is simplified and manufacturing is easier, but the diffusion of n-type dopants into vertical semiconductor channels becomes uneven due to large grain size and varying grain boundary orientations
Solution Approach 1:
The patent applies local quality by creating a composite semiconductor channel with two distinct regions: a pedestal channel portion with high dopant concentration and a vertical channel portion with low or zero dopant concentration. This local differentiation of dopant concentration within the channel structure enables precise control over dopant diffusion from the horizontal source contact layer, achieving uniform doping in the pedestal region while preventing excessive diffusion in the vertical channel region.
Solution Approach 2:
The semiconductor channel is segmented into two functional portions: a pedestal channel portion that contacts the source contact layer and receives dopants, and a vertical channel portion that extends upward with minimal dopant contamination. This segmentation allows each portion to have optimized dopant concentration for its specific function, resolving the contradiction between ease of manufacture with horizontal contact and precision of dopant distribution.
2Ease of manufacture
If polysilicon material with large grain size is used in the vertical semiconductor channel, then the material is easier to deposit and process, but the grain boundary orientations vary significantly leading to uneven dopant diffusion
Solution Approach 1:
The patent extracts the dopant-receiving function from the entire vertical channel and concentrates it in the pedestal channel portion. By separating the channel into a dopant-accepting pedestal region and a dopant-resistant vertical region, the invention removes the problem of uneven dopant diffusion from the vertical channel while maintaining the ease of using polysilicon material with large grain size for deposition.
3Device complexity
If uniform dopant concentration is maintained throughout the semiconductor channel, then the channel structure is simpler to manufacture, but the p-n junctions become diffuse rather than abrupt, degrading transistor performance
Solution Approach 1:
The patent implements local quality by establishing different dopant concentrations in different regions of the semiconductor channel. The pedestal channel portion has high dopant concentration to form abrupt p-n junctions with the source contact layer, while the vertical channel portion has low or zero dopant concentration. This local differentiation creates well-defined junction boundaries that improve transistor performance without significantly complicating the overall channel structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in improved source side select transistor performance, including better on/off ratios and gate-induced drain leakage (GIDL) erase operation, by controlling n-type dopant diffusion and forming a more abrupt junction.
Implementation Method 1
controlling the diffusion of n-type dopants into vertical semiconductor channels
Implementation Method 2
forming a more abrupt junction
Data Source
AI summary
A three-dimensional memory device includes a source contact layer overlying a substrate, an alternating stack of insulating layers and electrically conductive layers located overlying the source contact layer, and a memory opening fill structure located within a memory opening extending through the alternating stack and the source contact layer. The memory opening fill structure includes a composite semiconductor channel and a memory film laterally surrounding the composite semiconductor channel. The composite semiconductor channel includes a pedestal channel portion having controlled distribution of n-type dopants that diffuse from the source contact layer with a lower diffusion rate provided by carbon doping and smaller grain sizes, or has arsenic doping providing limited diffusion into the vertical semiconductor channel. The vertical semiconductor channel has large grain sizes to provide high charge carrier mobility, and is free of or includes only a low concentration of carbon atoms and n-type dopants therein.