Composite SiC Substrate Structure for High Resistivity and Low Warpage
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing silicon carbide (SiC) wafers with high resistivity and low warpage, as existing polycrystalline SiC wafers have low resistivity, limiting their use in high power applications and resulting in increased manufacturing costs and defects due to warpage issues.
Innovation Solution
A polycrystalline SiC substrate with a resistivity of at least 1*10^5 ohm-cm and low warpage is developed, featuring a monocrystalline SiC layer bonded to a polycrystalline SiC base substrate using surface activated bonding, with a grain size of 0.5 mm or greater, optimized for high power and frequency applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polycrystalline SiC wafers are manufactured with conventional methods, then manufacturing cost is reduced, but resistivity is low which limits use in high power applications
Solution Approach 1:
The patent creates a composite wafer structure by bonding a monocrystalline SiC layer to a polycrystalline SiC base substrate. The monocrystalline layer provides high resistivity (≥1×10^5 ohm-cm) necessary for high power applications, while the polycrystalline base substrate provides mechanical support and reduces manufacturing complexity. This composite approach allows the wafer to achieve high resistivity characteristics without requiring the entire substrate to be monocrystalline, thereby reducing manufacturing costs.
2Manufacturing precision
If polycrystalline SiC wafers are manufactured with conventional methods, then manufacturing complexity is reduced, but warpage is high which results in defects and cracked wafers
Solution Approach 1:
The patent controls the grain size parameter of the polycrystalline SiC base substrate to be ≥0.5 mm, which is a critical parameter change that reduces warpage. By optimizing this specific parameter (grain size) within the polycrystalline structure, the wafer achieves reduced warpage and fewer defects during processing, while maintaining the simpler polycrystalline manufacturing approach for the base substrate.
3Reliability
If monocrystalline SiC wafers are used, then resistivity is high, but manufacturing cost increases significantly
Solution Approach 1:
The patent applies local quality by providing high resistivity only in the specific region where it is needed (the monocrystalline SiC layer at the surface), while the bulk polycrystalline base substrate can have lower resistivity characteristics. This localized approach ensures that the high resistivity property is present where electrical performance is critical, while the rest of the wafer structure can be manufactured more economically using polycrystalline methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The high resistivity and low warpage of the substrate enable stable electrical performance and reduced defects in high power and frequency applications, enhancing the functionality and yield of electronic devices while reducing manufacturing costs by utilizing a less expensive polycrystalline SiC substrate as a support for a monocrystalline SiC layer.
Implementation Method 1
A polycrystalline SiC substrate with a resistivity of at least 1*10^5 ohm-cm and low warpage is developed, featuring a monocrystalline SiC layer bonded to a polycrystalline SiC base substrate using surface activated bonding
Data Source
AI summary
A polycrystalline SiC wafer or substrate with a high resistivity benefits functionality of a high power electronic or system in which the polycrystalline SiC wafer or substrate is present or is utilized in manufacturing the high power electronic or system. At least one embodiment of a wafer includes a polycrystalline SiC wafer or substrate that has a high resistivity (e.g., equal to or greater than 1*10{circumflex over ( )}5 or 1E+5 ohm-centimeters) and low warpage. Electronic devices or components made with or from the wafer including the high resistivity polycrystalline SiC wafer or substrate are further optimized when in use and have fewer to no crystal defects. The wafer formed according to the embodiments of the present disclosure has a high or very high resistivity as compared to existing polycrystalline SiC wafers or substrate.