Composite SOI Oxide Layer Structure for Low-Leakage Device Layers
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Solution Overview
Problem
Existing bond and etch processes for forming semiconductor-on-insulator (SOI) wafers result in bond interfaces that create leakage paths and affect the performance of semiconductor devices, and the use of thermal oxidation limits the use of epitaxial etch stop layers, leading to total thickness variation issues in the device layer.
Innovation Solution
A method involving a chemical vapor deposition (CVD) process to form a first oxide layer on the device layer, followed by bonding it with a second oxide layer formed via thermal oxidation, allowing for the removal of the donor wafer and etch stop layer, thereby positioning the bond interface away from the device layer and reducing total thickness variation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a bond and etch process is used to form SOI wafers, then the SOI structure is created, but bond interfaces are formed that create leakage paths and affect device performance
Solution Approach 1:
The patent extracts and removes the problematic bond interface from the final SOI structure. By forming the oxide layer on the handle wafer first, then bonding the device wafer to it, the bond interface is positioned within the handle wafer rather than within the device layer, effectively removing the source of leakage paths from the active device region.
Solution Approach 2:
The patent performs preliminary thermal oxidation to form the oxide layer on the handle wafer before bonding the device wafer. This preliminary action creates a stable, low-defect interface within the handle wafer, preventing subsequent leakage issues in the device layer.
2Manufacturing precision
If thermal oxidation is used to form the oxide layer, then the oxide layer is created, but the use of epitaxial etch stop layers is limited, leading to total thickness variation in the device layer
Solution Approach 1:
The patent segments the etch stop function from the oxide layer formation process. By using a separate epitaxial etch stop layer deposited on the device wafer before bonding, rather than relying on thermal oxidation alone, the patent enables precise thickness control of the device layer while maintaining the benefits of the oxide bonding process.
Solution Approach 2:
The patent employs a composite structure combining thermal oxide layer and epitaxial etch stop layer. The thermal oxide provides the bonding interface, while the epitaxial layer provides precise thickness control and etch stop functionality, achieving both low TTV and process versatility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces potential leakage paths and improves the performance of integrated chips by minimizing bond interface effects and enhancing the total thickness variation of the device layer.
Implementation Method 1
A method involving a chemical vapor deposition (CVD) process to form a first oxide layer on the device layer
Implementation Method 2
followed by bonding it with a second oxide layer formed via thermal oxidation
Data Source
AI summary
Various embodiments of the present disclosure are directed towards a semiconductor wafer. The semiconductor wafer comprises a handle wafer. A first oxide layer is disposed over the handle wafer. A device layer is disposed over the first oxide layer. A second oxide layer is disposed between the first oxide layer and the device layer, wherein the first oxide layer has a first etch rate for an etch process and the second oxide layer has a second etch rate for the etch process, and wherein the second etch rate is greater than the first etch rate.