Composite Spacer Structure for Sub-40 Nm Memory Alignment
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Solution Overview
Problem
In semiconductor manufacturing, particularly at technique nodes with feature sizes smaller than 40 nm, misalignment and overlay issues lead to degraded device performance and reduced yield.
Innovation Solution
The implementation of a composite spacer with a unique shape, featuring a bottom portion and a standing portion, along with a barrier structure, to address misalignment problems during the formation of storage devices such as MRAM, RRAM, or CBRAM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional spacer structures are used at feature sizes smaller than 40 nm, then manufacturing complexity is reduced, but misalignment and overlay issues occur leading to degraded device performance
Solution Approach 1:
The spacer structure is divided into multiple distinct portions: a first portion formed conformally on the sidewall of the trench, and a second portion formed subsequently to complete the spacer. This segmentation allows each portion to be optimized independently for its specific function, with the first portion providing initial structural support and the second portion ensuring proper alignment and dimensional control, thereby resolving the misalignment issues without requiring an overly complex monolithic structure
Solution Approach 2:
The first portion of the spacer is formed in advance before the second portion. This preliminary action establishes a foundation structure that guides subsequent processing steps, ensuring that when the second portion is formed, the alignment and dimensional control are already partially established, preventing misalignment and overlay issues in the final device
2Productivity
If feature size is reduced to increase device density, then productivity is improved, but misalignment issues degrade device performance and yield
Solution Approach 1:
The invention changes the dimensional parameters of the spacer structure by forming a first portion with specific thickness and a second portion with controlled dimensions. This parameter control ensures that even as feature sizes are reduced to increase device density, the spacer maintains sufficient thickness and proper dimensions to prevent misalignment and overlay issues, thereby maintaining manufacturing precision while enabling higher productivity through increased device density
3Manufacturing precision
If spacer thickness is increased to improve etching resistance, then manufacturing precision is improved, but device area increases reducing density
Solution Approach 1:
The spacer structure applies local quality by having a first portion with greater thickness providing enhanced etching resistance where needed, and a second portion that completes the structure with optimized dimensions. This localized differentiation allows the spacer to have sufficient etching resistance in critical areas without uniformly increasing the overall device area, thereby maintaining device density while improving manufacturing precision
Data Source
AI summary
A memory device includes a metal structure, a bottom electrode, a storage element, a top electrode, a first spacer, and a second spacer. The metal structure is embedded in a dielectric layer. The bottom electrode is disposed over the metal structure. The top electrode is disposed over the storage element. The first spacer interfaces a first sidewall of the top electrode. The first spacer has a topmost point lower than a topmost point of the top electrode in a cross-sectional view. The second spacer interfaces a second sidewall of the top electrode. The second spacer has a topmost point higher than the topmost point of the top electrode in the cross-sectional view.