Composite Stiffener Structure for CTE-Matched Semiconductor Packages
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Solution Overview
Problem
The increasing demand for high bandwidth memory in semiconductor packages leads to enlarged sizes, resulting in increased thermal stress due to differences in coefficient of thermal expansion (CTE), which complicates the manufacturing process and reduces yield.
Innovation Solution
A semiconductor package design incorporating a stiffener with a first metal layer, a core layer, and a second metal layer sequentially stacked, which helps to adjust and reduce thermal expansion coefficients, thereby mitigating thermal stresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of semiconductor packages is enlarged to accommodate more high bandwidth memory, then the storage capacity and bandwidth are improved, but the thermal stress increases due to difference in coefficient of thermal expansion (CTE)
Solution Approach 1:
The stiffener is constructed as a composite structure with a core layer (having CTE similar to circuit board) sandwiched between two metal layers (having high strength and stiffness). This composite design allows the stiffener to simultaneously provide mechanical reinforcement and thermal expansion compatibility, reducing thermal stress in enlarged semiconductor packages while maintaining structural integrity.
Solution Approach 2:
The patent adjusts the coefficient of thermal expansion parameter by selecting materials with appropriate CTE values for different layers of the stiffener. The core layer is specifically chosen to have CTE matching the circuit board, while metal layers are selected for their mechanical properties, creating a balanced structure that mitigates thermal stress through parameter optimization.
2Quantity of substance
If the size of semiconductor packages is enlarged, then the storage capacity is improved, but the manufacturing process difficulty increases
Solution Approach 1:
The composite stiffener structure with differentiated layers (core layer with CTE-matching material and metal layers with high strength) enables the package to accommodate larger sizes without proportionally increasing process difficulty. The modular layered design simplifies manufacturing by allowing each layer to be optimized independently for its specific function.
3Quantity of substance
If the size of semiconductor packages is enlarged, then the storage capacity is improved, but the yield decreases
Solution Approach 1:
The stiffener's composite structure with CTE-matched core layer and high-strength metal layers reduces thermal stress and improves reliability in enlarged packages, directly addressing yield reduction issues. The design ensures that as package size increases, the structural integrity and stress distribution remain controlled, maintaining higher yield rates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces thermal stresses and production costs by aligning the thermal expansion of the stiffener with the circuit board, improving the manufacturing process and yield of semiconductor packages.
Implementation Method 1
the core layer may include an organic material having a coefficient of thermal expansion (CTE) matched to that of the circuit board
Implementation Method 2
the first metal layer and the second metal layer may each include at least one of copper (Cu), aluminum (Al), or an alloy thereof
Data Source
AI summary
Provided is a semiconductor package including a stiffener. The semiconductor package comprises a circuit board, a semiconductor chip on the circuit board, and a stiffener around the semiconductor chip, wherein the stiffener includes a first metal layer, a core layer, and a second metal layer sequentially stacked.