Composite Strain Structure for Transistor Channel Stress
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Solution Overview
Problem
Conventional transistors with single silicon-germanium source and drain layers face challenges in providing sufficient compressive stress to the channel as device geometries scale below 65 nm, leading to reduced electrical efficiency and performance.
Innovation Solution
The implementation of a composite strain structure with a first and second strain region, where the second strain region provides a larger stress volume, disposed adjacent to the channel below the gate electrode, enhancing compressive or tensile stress and improving electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device geometries are scaled below 65 nm to improve integration density, then productivity increases, but electrical efficiency deteriorates due to insufficient compressive stress in single strain layers
Solution Approach 1:
The single strain layer is segmented into multiple strain layers (first strain layer and second strain layer) with different crystal orientations. The first strain layer has a first crystal orientation and the second strain layer has a second crystal orientation different from the first, allowing each layer to contribute differently to the compressive stress on the channel, thereby maintaining electrical efficiency at scaled dimensions
Solution Approach 2:
The patent employs a composite strain structure combining multiple strain layers with different crystal orientations and material compositions. This composite approach enables the structure to provide enhanced and more uniform compressive stress to the channel region, resolving the electrical efficiency degradation that occurs when device geometries are scaled below 65 nm
2Device complexity
If a single silicon-germanium strain layer is used to provide compressive stress, then device complexity is reduced, but the stress volume becomes insufficient at scaled dimensions, worsening electrical performance
Solution Approach 1:
The strain structure is divided into multiple discrete strain layers rather than using a single continuous layer. Each layer can be independently optimized for thickness, composition, and crystal orientation, allowing the overall structure to provide sufficient stress volume even as device dimensions scale down, while maintaining manageable complexity through modular design
Solution Approach 2:
The patent introduces an additional dimension of crystal orientation variability by using strain layers with different crystal orientations. This dimensional addition to the strain structure allows for enhanced stress distribution and volume without proportionally increasing structural complexity, as the different orientations provide complementary stress contributions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The composite strain structure increases the relative drive current gain by about 10% compared to conventional transistors, enhancing electronic mobility and current efficiency, particularly in PMOS transistors formed using 22-nm technology.
Implementation Method 1
a strained silicon-germanium layer has been proposed to provide a compressive stress to a channel of a transistor for providing a desired electronic mobility
Data Source
AI summary
A transistor includes a gate electrode disposed over a substrate. At least one composite strain structure is disposed adjacent to a channel below the gate electrode. The at least one composite strain structure includes a first strain region within the substrate. A second strain region is disposed over the first strain region. At least a portion of the second strain region is disposed within the substrate.