Composite Intervening Structure for 3D Optical Semiconductor Stacks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The scaling down of optical semiconductor devices poses challenges in achieving improved quality, yield, performance, and reliability while reducing complexity, particularly in signal transfer and energy consumption.
Innovation Solution
The design incorporates a logic die, a memory die, and a sensor die with specific inter-die and intra-die vias that electrically couple to simplify the sensor die's fabrication and reduce signal path length, allowing for efficient signal transfer and storage of intermediate processing signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the sensor die includes complex circuits for signal processing, then the processing capability is improved, but the fabrication complexity and device complexity increase
Solution Approach 1:
The device is divided into three separate functional dies: sensor die (for light sensing), memory die (for signal storage), and logic die (for signal processing). This segmentation allows each die to be optimized independently, simplifying the sensor die fabrication while maintaining comprehensive signal processing capability through the logic die.
Solution Approach 2:
The memory die acts as an intermediary between the sensor die and logic die. It receives raw signals from the sensor die via inter-die vias and stores them temporarily, allowing the logic die to process signals without requiring complex circuits on the sensor die itself.
2Adaptability or versatility
If the signal path between sensor die and logic die is lengthened for intermediate processing, then the processing stages are improved, but the energy consumption increases
Solution Approach 1:
The signal transfer is optimized by stacking dies vertically in a 3D configuration rather than placing them side-by-side in 2D. This vertical arrangement significantly shortens the physical distance signals must travel between sensor, memory, and logic functions, reducing energy consumption while maintaining multi-stage processing capability.
3Productivity
If the optical semiconductor device is scaled down to improve computing ability, then the integration density is improved, but the quality, yield, and reliability deteriorate
Solution Approach 1:
By segmenting the device into separate functional dies that can be fabricated independently using optimized processes for each function, the patent achieves high integration density through 3D stacking while maintaining high yield and reliability. Each die can be manufactured with process parameters optimized for its specific function, avoiding the compounding defects that would result from scaling down a monolithic integrated circuit.
Data Source
AI summary
The present application provides an optical semiconductor device with a composite intervening structure. The optical semiconductor device includes a logic die including a core circuit area and a logic peripheral circuit area; a memory die positioned on the logic die and including a memory cell area and a memory peripheral area, and a first inter-die via positioned in the memory peripheral area and electrically connected to the logic peripheral circuit area; and a sensor die positioned on the memory die and including a sensor pixel area and a sensor peripheral area, a first intra-die via positioned in the sensor peripheral area and electrically coupled to the logic peripheral circuit area through the first inter-die via, and a second intra-die via positioned in the sensor peripheral area. The intervening structure is disposed on the back surface of the memory die.