Composite Substrate Stacking for Fine-Pitch Chip Interconnects
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Solution Overview
Problem
Conventional methods for electronic device assemblies face challenges in achieving high bandwidth chip-to-chip interconnections, fine pitch wiring, and adequate thermal expansion matching, leading to mechanical reliability and assembly yield limitations, especially with large chips and interposers having high coefficients of thermal expansion (CTE) mismatches.
Innovation Solution
A composite substrate with a base substrate having a CTE between 3 and 12 ppm/°C, featuring high-density substrate layers with fine pitch wiring and vias, and optional high-k layers with embedded decoupling capacitors, allowing for direct stacking and integration of multiple chips with improved thermal and mechanical support, using metal posts and interconnect layers for secure bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional substrates with high CTE (coefficient of thermal expansion) are used for large chips and interposers, then the substrate can support large area and high density interconnections, but thermal expansion mismatch causes mechanical reliability problems and assembly yield limitations
Solution Approach 1:
The patent changes the CTE parameter of the substrate material from conventional high CTE values to a controlled range of 3-12 ppm/°C. This parameter change allows the substrate to maintain large area (greater than 25mm×25mm) while achieving thermal expansion compatibility with semiconductor chips, thereby resolving the mechanical reliability issues caused by CTE mismatch during thermal cycling and assembly processes
Solution Approach 2:
The patent employs composite substrate structures including organic substrates with controlled CTE, thin film organic layers, molded organic materials, silicon or glass interposers with through-silicon vias (TSV) or through-glass vias (TGV), and ceramic substrates. These composite materials achieve both large area support and matched thermal expansion properties, resolving the contradiction between substrate size and mechanical reliability
2Manufacturing precision
If fine pitch wiring with less than 2 micron to 10 micron width and spacing is implemented, then high bandwidth interconnections are achieved, but manufacturing precision and assembly difficulty increase
Solution Approach 1:
The patent segments the substrate structure into multiple functional layers including base substrate, organic layers, interposer layers with TSV/TGV, and wiring layers. This segmentation allows fine pitch wiring (2-10 micron width and spacing) to be implemented in specific layers while other layers provide mechanical support and thermal management, making the overall manufacturing process more manageable despite the high precision requirements
Solution Approach 2:
The patent introduces intermediary structures such as thin film organic layers, molded organic layers, and interposer layers with via structures that serve as mediators between the fine pitch wiring layers and the base substrate. These intermediaries provide mechanical support, stress relief, and alignment references that facilitate the manufacturing of high-precision fine pitch wiring
3Productivity
If direct stacking of chips and substrates is implemented for high bandwidth interconnection, then integration density is improved, but thermal management and CTE matching become more challenging
Solution Approach 1:
The patent designs the substrate and interposer structures to serve multiple functions simultaneously: providing mechanical support, enabling fine pitch electrical interconnections, managing thermal expansion through controlled CTE (3-12 ppm/°C), and facilitating thermal management. This multi-functionality allows direct stacking of chips and substrates for high integration density while addressing thermal challenges through the same structural elements
Solution Approach 2:
The patent explicitly addresses thermal expansion by controlling the CTE of substrate materials to match semiconductor chips (3-12 ppm/°C). This thermal expansion matching prevents warpage and mechanical failure during thermal cycling, enabling reliable direct stacking of multiple chips and substrates for high bandwidth interconnection without compromising thermal management
Data Source
AI summary
A base substrate, high-k substrate layers on the base substrate with discrete decoupling capacitors embedded, high density substrate layers on the high-k substrate layers supporting wiring and wiring spacing of less than 2 up to about 10 micron width, pitch connectivity between the upper surface of the base substrate and a lower surface of the set of high density substrate layers supports less than 50 up to about 300 micron pitch, the pitch connectivity on an upper surface of the set of high density substrate layers supports less than about 150 micron pitch. A method including attaching a set of metal posts at each contact on a lower surface of a set of high density substrate layers, attaching to a handler, attaching an interconnect layer to a base substrate, and attaching the set of high density substrate layers to the base substrate while aligning each metal post with a contact.